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參數(shù)資料
| 型號(hào)： | FS8160 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC |
| 中文描述： | 1.1 GHz/1.1 GHz雙鎖相環(huán)集成電路 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 257K |
| 代理商： | FS8160 |
FS8160
Page 8
April 2003
cated below.
The definition of the contents of the shift register relating to each particular latch location
is listed in the table below.
The 12-bit main and auxiliary reference (
R
) divider ratios are specified by the
MAINR[11:0] and AUXR[11:0] bits, respectively, and are defined in the table below.
Table 1: Latch enable control bits
CB[1]
CB[0]
Latch Location
0
0
Aux. R
0
1
Aux. N
1
0
Main R
1
1
Main N
Table 2: Serial data input format
First
bit
Shift Register Bit Location
Last
bit
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Aux. R
FOLD[3:0]
AUXR[11:0])
0
0
Aux. N
AUXB[11:0]
AUXA[3:0]
0
1
Main R
CP_CNTRL[3:0]
MAINR[11:0]
1
0
Main N
MAINB[11:0]
MAINA[3:0]
1
1
Table 3: Reference divider ratios
Divide
Ratio
MAINR[11:0] and AUXR[11:0]
11
10
9
8
7
6
5
4
3
2
1
0
2
0
0
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
0
1
1
4095
1
1
1
1
1
1
1
1
1
1
1
1
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