- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358706 > FM25L16-DG (Electronic Theatre Controls, Inc.) 4Kb FRAM Serial 3V Memory PDF資料下載
參數(shù)資料
FM25L16
Rev. 2.0
Mar. 2005
Page 5 of 14
Data Transfer
All data transfers to and from the FM25L16 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L16. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by an address and one
or more bytes of data.
Table 1. Op-code Commands
Name
Description
WREN
Set Write Enable Latch
WRDI
Write Disable
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read Memory Data
WRITE
Write Memory Data
Op-code
0000
0110b
0000
0100b
0000
0101b
0000
0001b
0000
0011b
0000
0010b
WREN - Set Write Enable Latch
The FM25L16 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FM25L16-G | 4Kb FRAM Serial 3V Memory |
| FMS2007-000-EB | DC-6GHz DPDT Diversity Switch |
| FMS2007QFN | DC-6GHz DPDT Diversity Switch |
| FMS2007-001-EB | DC-6GHz DPDT Diversity Switch |
| FMS2007 | DC-6GHz DPDT Diversity Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM25L16-DGTR | 功能描述:F-RAM 16K (2Kx8) 2.7V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM25L16-G | 功能描述:F-RAM 16K (2Kx8) 2.7V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM25L16-GA | 功能描述:F-RAM 16K (2Kx8) 2.7V Grade 3 AEC-Q100 RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM25L16-GATR | 功能描述:F-RAM 16K (2Kx8) 2.7V Grade 3 AEC-Q100 RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM25L16-GTR | 功能描述:F-RAM 16K (2Kx8) 2.7V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。