參數(shù)資料
型號: FLF Series
英文描述: High Density FLASH Memory Card 16, 32, 48, 64, 80 MB(16, 32, 48, 64, 80 M字節(jié)高密度閃速存儲器卡)
中文描述: 高密度閃存卡16,32,48,64,80 MB的(16,32,48,64,80米字節(jié)高密度閃速存儲器卡)
文件頁數(shù): 5/13頁
文件大?。?/td> 154K
代理商: FLF SERIES
June 2000 Rev. 3 - ECO #12871
5
PCMCIA Flash Memory Card
FLF Series
PC Card Products
Card Interface
The FLF series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining
PCMCIA compatibility, the FLF series card has integrated special features to extend functionality.
Card has built in 2 control registers:
- Configuration Option Register (COR)
Address = 4000
h
- Configuration and Status Register (CSR)
Address = 4002
h
COR register:
provide a soft reset function (bit D7) and additional page register (bit D0) to extend card
capacity beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state all
memory devices are place in power down mode, minimizing power consumption. Returning this bit to 0
leaves the reset cycle and place the card in the same condition as following a power up or hardware reset.
This bit must be cleared to 0, to access any device on the card.
Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit:
1. Initialization: write 1 to SReset
- reset cycle begin
- memory devices enters Power-Down mode aborting all operations and clearing all
registers.
2. Write 0 to SReset
- Reset cycle ends
- memory devices and registers enters power on default state
Card can be place in Power Down mode by activating Reset signal (pin58) or by controlling the bit D2 in
CSR register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend
card capacity beyond 64MB.
Only bit D0 is supported:
- D0 set to 0 selects
page 0
- D0 set to 1 selects:
page 1
D0 is set to the value of 0, during power on or any reset.
CSR register:
provide a power control of memory array. Only bit D2 is supported; all other bits are “don’t
care”
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by
asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode.
Card Information Structure (CIS) contains information about Registers addressing and Memory structure.
Cards with memory capacity < 64MB do not support Configuration Index bits.
Notes:
1. Reading from undefined address location or unsupported bits will return random data.
2. Writing to undefined address location may result in card malfunctioning due to limited address
decoding.
3. See block diagram for more details about control registers.
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