2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN424C / FIN425C Rev. 1.0.0
3
SerD
es
FIN
4
24C
/
FIN
425C
—
20-
B
it
U
lt
ra-
Low-
P
ower
Serializer
/
D
eserializer
f
o
rC
ont
roller
and
R
G
B
D
isplays
FIN425C Deserializer Pin Descriptions
Pin Name
Description
WCLK
LVCMOS STRB Output
DP[19:0]
LVCMOS Data Output
/RES
Low-Power Mode
0 Deserializer Low Power
1 Deserializer Enabled
SLEW
Parallel Output Edge Rate Control
0 Slow Output Edge Rates
1 Fast Output Edge Rates
Test
Internal Use (Should be GND)
DS+, DS-
Serial Data Input
CKS+, CKS-
Serial Clock Input
VDDP
Power Supply for Parallel I/O and internal circuitry
VDDS
Power Supply for Serial I/O
VDDA
Power Supply for Core
GND
Ground Pins
Notes:
3.
0 = VIL; 1 = VIH.
4.
All GND and VDDP pins must be connected to ground and VDDP, respectively.
11
12
13
14
15
31
30
28
27
26
25
GN D PA D
M ust be G rounded
CKS+
DP[12]
DP[11]
DP[10]
VDD P
DP[9]
DP[8]
DP[7]
DP[6]
D
P
[19]
D
P
[18]
D
P
[17]
D
P
[16]
DP[
15
]
WC
LK
DP[
14
]
DP[
13
]
DP
[0
]
DP
]
DP
[2
]
DP
[3
]
DP
[4
]
DP
[5
]
1
CKS- 2
4
V DD S
V DD A
3
DS- 5
DS+ 6
/R ES 7
V DD P 8
10
Te
st
9
SL
E
W
32
20
21
19
23
18
16
17
22
24
29
11
12
13
14
15
31
30
28
27
26
25
GN D PA D
M ust be G rounded
CKS+
DP[12]
DP[11]
DP[10]
VDD P
DP[9]
DP[8]
DP[7]
DP[6]
D
P
[19]
D
P
[18]
D
P
[17]
D
P
[16]
DP[
15
]
WC
LK
DP[
14
]
DP[
13
]
DP
[0
]
DP
[1
]
DP
[2
]
DP
[3
]
DP
[4
]
DP
[5
]
1
CKS- 2
4
V DD S
V DD A
3
DS- 5
DS+ 6
/R ES 7
V DD P 8
10
9
SL
E
W
32
20
21
19
23
18
16
17
22
24
29
Figure 3.
FIN425CMLX MLP-32 Pinout (Top Through View)
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