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參數(shù)資料
| 型號： | FIN224ACGFX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER/DESERIALIZER 42BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 676Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 22 |
| 輸出數(shù)： | 22 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 42-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 42-BGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1217 (CN2011-ZH PDF) |
| 其它名稱： | FIN224ACGFXDKR |
SC16IS740_750_760
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 9 June 2011
18 of 63
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.8 Programmable baud rate generator
The SC16IS740/750/760 UART contains a programmable baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (216 –1). An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as
shown in Figure 15. The output frequency of the baud rate generator is 16
the baud
rate. The formula for the divisor is given in Equation 1:
(1)
where:
prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 15 shows the internal prescaler and baud rate generator circuitry.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
1.8432 MHz and 3.072 MHz, respectively. The crystal’s frequency tolerance should be
selected as such to keep the baud rate error to be below 1 % for reliable operation with
other UARTs. Crystals with
100 ppm is generally recommended.
Figure 16 shows the crystal clock circuit reference.
Fig 15. Prescaler and baud rate generator block diagram
divisor
XTAL1 crystal input frequency
prescaler
-----------------------------------------------------------------------------------
desired baud rate
16
-----------------------------------------------------------------------------------------
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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