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參數(shù)資料
| 型號： | FIN12AC |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary) |
| 中文描述： | 低電壓12位雙向串行器/有多個頻率范圍串器（初步） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 1819K |
| 代理商： | FIN12AC |
Preliminary
7
www.fairchildsemi.com
F
Embedded Word Clock Operation
The FIN12AC sends and receives serial data source syn-
chronously with a bit clock. The bit clock has been modified
to create a word boundary at the end of each data word.
The word boundary has been implemented by skipping a
low clock pulse. This appears in the serial clock stream as
3 consecutive bit times where signal CKSO remains HIGH.
In order to implement this sort of scheme two extra data
bits are required. During the word boundary phase the data
will toggle either HIGH-then-LOW or LOW-then-HIGH
dependent upon the last bit of the actual data word. Table
provides some examples showing the actual data word and
the data word with the word boundary bits added. Note that
a 12-bit word will be extended to 14 bits during serial trans-
mission. Bit 13 and Bit 14 are defined with-respect-to Bit
12. Bit 13 will always be the inversion of Bit 12 and Bit 14
will always be the same as Bit 12. This insures that a
“
0
”
o
“
1
”
and a
“
1
”
o
“
0
”
transition will always occur during the
embedded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits and
the boundary clock condition and embeds them into the
serial data stream. The deserializer looks for the end of the
word boundary condition to capture and transfer the data to
the parallel port. The deserializer only uses the embedded
word boundary information to find and capture the data.
These boundary bits are then stripped prior to the word
being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value
equal to
of V
DDP
. The input buffers are only operational
when the device is operating as a serializer. When the
device is operating as a deserializer the inputs are gated
off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2 mAs at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH the bi-directional LVCMOS I/
Os will be in HIGH-Z state. Under purely capacitive load
conditions the output will swing between GND and V
DDP
.
The LVCMOS I/O buffers incorporate bushold functionality
to allow for pins to maintain state when they are not driven.
The bushold circuitry only consumes power during signal
transitions.
FIGURE 6. LVCMOS I/O
Differential I/O Circuitry
. The FIN12AC employs FSC proprietary CTL I/O technol-
ogy. CTL is a low power, low EMI differential swing I/O
technology. The CTL output driver generates a constant
output source and sink current. The CTL input receiver
senses the current difference and direction from the corre-
sponding output buffer to which it is connected. This differs
from LVDS which uses a constant current source output
but a voltage sense receiver. Like LVDS an input source
termination resistor is required to properly terminate the
transmission line. The FIN12AC device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input receiver.
The gated termination resistor insures proper termination
regardless of direction of data flow. The relative greater
sensitivity of the current sense receiver of CTL allows it to
work at much lower current drive and correspondingly a
much lower voltage.
During power-down mode the differential inputs will be dis-
abled and powered down and the differential outputs will be
placed in a HIGH-Z state. CTL inputs have an inherent fail-
safe capability that supports floating inputs. When the CKSI
input pair of the serializer is unused it can reliably be left
floating. Alternately both of the inputs can be connected to
ground. CTL inputs should never be connected to V
DD
.
When the CKSO output of the deserializer is unused it
should be allowed to float.
FIGURE 7. Bi-directional Differential I/O Circuitry
12 Bit Data Words
12 Bit Data Word with Word Boundary
Hex
2FFFh
10 1111 1111 1111b
1555h
01 0101 0101 0101b
1xxxh
01 0xxx xxxx xxxxb
2xxxh
10 1xxx xxxx xxxxb
Hex
FFFh
555h
xxxh
xxxh
Binary
Binary
1111 1111 1111b
0101 01010 0101b
0xxx xxxx xxxxb
1xxx xxxx xxxxb
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FIN12ACMLX | Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary) |
| FIN1531M | 5V LVDS 4-Bit High Speed Differential Driver |
| FIN1531MTC | 5V LVDS 4-Bit High Speed Differential Driver |
| FIN1531MTCX | LINE DRIVER|4 DRIVER|CMOS|TSSOP|16PIN|PLASTIC |
| FIN1531MX | LINE DRIVER|4 DRIVER|CMOS|SOP|16PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FIN12AC_06 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges |
| FIN12AC_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges |
| FIN12ACGFX | 功能描述:LVDS 接口集成電路 LVDS 21Bit Serializr De-Serializer RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| FIN12ACMLX | 功能描述:LVDS 接口集成電路 INTERFACE RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| FIN12Y WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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