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參數(shù)資料
| 型號： | FIN1108MTDX |
| 英文描述： | REPEATER INTERFACE|TSSOP|48PIN|PLASTIC |
| 中文描述： | 中繼器接口|采用TSSOP | 48PIN |塑料 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 408K |
| 代理商： | FIN1108MTDX |
Preliminary
3
www.fairchildsemi.com
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3:
All typical values are at T
A
=
25
°
C and with V
CC
=
3.3V.
Note 4:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 5:
Passing criteria for maximum frequency is the output V
OD
>
250 mV and the duty cycle is better than 45% / 55% with all channels switching.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
t
PLHD
Differential Propagation Delay
LOW-to-HIGH
0.8
1.8
ns
t
PHLD
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
R
L
=
100
, C
L
=
5 pF,
V
ID
=
100 mV to 1100 mV,
V
IC
=
V
ID
/2 to V
CC
(V
ID
/2),
Duty Cycle
=
50%,
See Figure 3 and Figure 4
0.8
1.8
ns
t
TLHD
t
THLD
t
SK(P)
t
SK(PP)
f
MAX
t
PZHD
t
PZLD
t
PHZD
t
PLZD
t
DJ
0.29
0.58
ps
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Part-to-Part Skew (Note 4)
0.29
0.58
0.2
0.5
ps
ns
ns
Maximum Frequency (Note 5)
Differential Output Enable Time from Z to HIGH
Differential Output Enable Time from Z to LOW
800
Mbps
ns
ns
10
10
R
L
=
100
, C
L
=
5 pF,
Differential Output Disable Time from HIGH to Z See Figure 5 and Figure 6
Differential Output Disable Time from LOW to Z
LVDS Data Jitter,
10
10
ns
ns
V
ID
=
300 mV, PRBS
=
2
23
1,
V
IC
=
1.2V at 800 Mbps
V
ID
=
300 mV
V
IC
=
1.2 V at 400 MHz
100
135
ps
Deterministic
LVDS Clock Jitter, Random
(RMS)
t
RJ
2.2
3.5
ps
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