參數(shù)資料
型號: FIN1102MTC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: LVDS 2 Port High Speed Repeater
中文描述: DUAL LINE TRANSCEIVER, PDSO14
封裝: 4.40 MM, MO-153, TSSOP-14
文件頁數(shù): 3/5頁
文件大?。?/td> 320K
代理商: FIN1102MTC
3
www.fairchildsemi.com
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3:
All typical values are at T
A
=
25
°
C and with V
CC
=
3.3V, V
ID
=
300 mV, V
IC
=
1.2V, unless otherwise specified.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
Passing criteria for maximum frequency is the output V
OD
>
200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 7:
Output loading is transmission line environment only; C
L
is
<
1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency
=
10 MHz, t
R
or
t
F
<
=
0.5 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
t
PLHD
Differential Output Propagation Delay
LOW-to-HIGH
0.75
1.1
1.75
ns
t
PHLD
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%) |V
ID
|
=
200 mV to 450 mV,
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
0.75
1.1
1.75
ns
R
L
=
100
, C
L
=
5 pF,
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
PZHD
0.29
0.4
0.58
ns
V
IC
=
|V
ID
|/2 to V
CC
(|V
ID
|/2),
Duty Cycle
=
50%,
See Figure 3 and Figure 4
0.29
0.4
0.02
0.02
0.58
0.2
ns
ns
0.15
ns
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
0.02
0.5
ns
MHz
400
800
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
2.3
5
ns
t
PZLD
2.5
5
ns
from Z to LOW
Differential Output Disable Time
from HIGH to Z
R
L
=
100
, C
L
=
5 pF,
See Figure 5 and Figure 6
t
PHZD
1.6
5
ns
t
PLZD
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
1.9
5
ns
t
DJ
|V
ID
|
=
300 mV, PRBS
=
2
23
- 1,
V
IC
=
1.2V at 800 Mbps
|V
ID
|
=
300 mV,
V
IC
=
1.2V at 400 MHz
85
135
ps
Deterministic
LVDS Clock Jitter,
Random (RMS)
t
RJ
2.1
3.5
ps
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