參數(shù)資料
型號(hào)： FAN5069MTCX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： PWM and LDO Controller Combo
中文描述： 0.15 A SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16
封裝： LEAD FREE, TSSOP-16
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 379K
代理商： FAN5069MTCX
13
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
Where I
Ripple
is the ripple current.
Typically this number varies between 20% to 50% of the maxi-
mum steady state load on the converter.
When selecting an inductor from the vendors, select the induc-
tance value which is close to the value calculated at the rated
current (including half the ripple current).
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS current rating
to withstand the temperature rise caused by the internal power
dissipation. The combined RMS current rating for the input
capacitor should be greater than the value calculated using the
following equation:
(EQ. 7)
Common capacitor types used for such application include alu-
minum, ceramic, POS CAP, and OSCON.
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough ESR to
meet the output ripple and load transient requirements. The
ESR of the output capacitor should be lower than both of the
values calculated below to satisfy both the transient loading and
steady state ripple conditions as given by the following equation:
(EQ. 8)
Typically, in case of aluminum and polymer based capacitors,
the output capacitance is higher than normally required to meet
these requirements. While selecting the ceramic capacitors for
the output, although lower ESR can be achieved easily, higher
capacitance values are required to meet the V
OUT(MIN)
restric-
tions during a load transient. From the stability point of view, the
zero caused by the ESR of the output capacitor plays an impor-
tant role in the stability of the converter.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100μF with
ESR around 100m
Ω
is recommended. For other values, contact
the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs as cir-
cuit switch elements. For better performance, the MOSFET
selection should address the following key parameters:
■
The maximum drain to source voltage should be at least 25%
higher than the worst-case input voltage.
■
The MOSFETs chosen should have low Q
G
, Q
GD,
and Q
GS
■
The R
DS_ON
of the MOSFETs be as low as possible.
In typical applications for a buck converter, the duty cycles are
lower than 20%. So, to optimize the selection of MOSFETs for
both the high-side and low-side, follow different selection crite-
ria. Select the high-side MOSFET to minimize the switching
losses and the low-side MOSFET to minimize the conduction
losses due to the channel and the body diode losses. Note that
the gate drive losses also affect the temperature rise on the
controller.
For loss calculation, refer to Fairchild's Application Note AN-
6005 and the associated Excel spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following switch-
ing interval of the MOSFET as shown in Figure 22. MOSFET
Gate drive equivalent circuit is shown in Figure 23.
Figure 22. Switching Losses and Q
G
Figure 23. Drive Equivalent Circuit
The upper graph in Figure 22 represents Drain-to-Source Volt-
age (V
DS
) and Drain Current (I
D
) waveforms. The lower graph
details Gate-to-Source Voltage (V
GS
) vs. time with a constant
current charging the gate. The x-axis therefore is also represen-
tative of Gate Charge (Q
G
). C
ISS
= C
GD
+ C
GS
, and it controls
t1, t2, and t4 timing. C
GD
receives the current from the gate
driver during t3 (as VDS is falling). Obtain the gate charge (Q
G
)
parameters shown on the lower graph from the MOSFET data
sheets.
Assuming switching losses are about the same for both the ris-
ing edge and falling edge, Q1's switching losses occur during
the shaded time when the MOSFET has voltage across it and
current through it.
These losses are given by (EQ. 9), (EQ. 11), and (EQ. 11):
P
UPPER
= P
SW
+ P
COND
(EQ. 9)
(EQ. 10)
(EQ. 11)
Where:
P
UPPER
is the upper MOSFET's total losses, and P
SW
and
P
COND
are the switching and conduction losses for a given
I
INPUT RMS
(
)
I
LOAD MAX
(
)
=
V
IN
---------------
V
IN
---------------
2
–
×
ESR
V
LOAD MAX
(
)
-------------------------------------
≤
and ESR
V
Ripple
--------------------
≤
V
SP
V
TH
V
GS
t1
t2
t3
4.5V
t4
t5
G(SW)
V
DS
I
D
Q
GS
Q
GD
C
ISS
C
GD
C
ISS
Q
C
GD
R
D
G
R
GATE
C
GS
HDRV
5V
SW
VIN
P
SW
V
----------------------
I
L
×
2
2
t
s
×
×
F
SW
=
P
COND
V
IN
---------------
I
OUT
2
R
DS ON
)
×
×
=
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