參數(shù)資料
型號(hào)： F28F010-90
廠商： INTEL CORP
元件分類： DRAM
英文描述： 1024K (128K x 8) CMOS FLASH MEMORY
中文描述： 128K X 8 FLASH 12V PROM, 90 ns, PDSO32
封裝： 0.310 X 0.720 INCH, REVERSE, TSOP-32
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 405K
代理商： F28F010-90
28F010
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays. Intel provides two read-control inputs to ac-
commodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an ad-
dress-decoder output should drive chip-enable,
while the system’s read signal controls all flash-
memories and other parallel memories. This assures
that only enabled memory devices have active out-
puts, while deselected devices maintain the low
power standby condition.
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling. System designers
are interested in three supply current (I
CC
) issuesD
standby, active, and transient current peaks pro-
duced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1
m
F ceramic capacitor
connected between V
CC
and V
SS
, and between V
PP
and V
SS
.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7
m
F electrolytic capaci-
tor should be placed at the array’s power supply
connection, between V
CC
and V
SS
. The bulk capaci-
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
V
PP
Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
PP
power sup-
ply trace. The V
PP
pin supplies the memory cell cur-
rent for programming. Use similar trace widths and
layout considerations given the V
CC
power bus. Ad-
equate V
PP
supply traces and decoupling will de-
crease V
PP
voltage spikes and overshoots.
Power Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is indifferent
as to which power supply, V
PP
or V
CC
, powers up
first. Power supply sequencing is not required. Inter-
nal circuitry in the 28F010 ensures that the com-
mand register is reset to the read mode on power
up.
A system designer must guard against active writes
for V
CC
voltages above V
LKO
when V
PP
is active.
Since both WE
Y
and CE
Y
must be low for a com-
mand write, driving either to V
IH
will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory con-
tents only occurs after successful completion of the
two-step command sequences.
28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.
Table 4. 28F010 Typical Update Power Dissipation
(4)
Operation
Notes
Power Dissipation
(Watt-Seconds)
Array Program/Program Verify
1
0.171
Array Erase/Erase Verify
2
0.136
One Complete Cycle
3
0.478
NOTES:
1. Formula to calculate typical Program/Program Verify Power
e
[
V
PP
c
Y
Bytes
c
typical
Y
Prog Pulses (t
WHWH1
c
I
PP2
typical
a
t
WHGL
c
I
PP4
typical)
]
a
[
V
CC
c
Y
Bytes
c
typical
Y
Prog Pulses (t
WHWH1
c
I
CC2
typical
a
t
WHGL
c
I
CC4
typical
]
.
2. Formula to calculate typical Erase/Erase Verify Power
e
[
V
PP
(V
PP3
typical
c
t
ERASE
typical
a
I
PP5
typical
c
t
WHGL
c
Y
Bytes)
]
a
[
V
CC
(I
CC3
typical
c
t
ERASE
typical
a
I
CC5
typical
c
t
WHGL
c
Y
Bytes)
.
3. One Complete Cycle
e
Array Preprogram
a
Array Erase
a
Program.
4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
13
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