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參數(shù)資料
| 型號： | F28F010-65 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 1024K (128K x 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 65 ns, PDSO32 |
| 封裝： | 0.310 X 0.720 INCH, REVERSE, TSOP-32 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 405K |
| 代理商： | F28F010-65 |
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28F010
290207–6
Bus
Command
Comments
Operation
Entire Memory Must
e
00H
Before Erasure
Use Quick Pulse
Programming Algorithm
(Figure 5)
Standby
Wait for V
PP
Ramp to V
PPH
(1)
Initialize Addresses and
Pulse-Count
Write
Set-up
Erase
Data
e
20H
Write
Erase
Data
e
20H
Standby
Duration of Erase Operation
(t
WHWH2
)
Write
Erase
(2)
Verify
Addr
e
Byte to Verify;
Data
e
A0H; Stops Erase
Operation
(3)
t
WHGL
Standby
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Data
e
00H, Resets the
Register for Read Operations
Standby
Wait for V
PP
Ramp to V
PPL
(1)
1. See DC Characteristics for the value of V
PPH
and
V
PPL
.
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice.
Figure 6. 28F010 Quick Erase Algorithm
12
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