參數(shù)資料
型號: F25L008A
廠商: Elite Semiconductor Memory Technology Inc.
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 24/31頁
文件大小: 374K
代理商: F25L008A
ES MT
TABLE 11: RELIABILITY CHARACTERISTICS
F25L008A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.4
24/31
Publication Date
:
May. 2007
Symbol
Parameter
Minimum Specification
Units
Test Method
N
END
1
Endurance
100,000
Cycles
JEDEC Standard A117
T
DR
1
Data Retention
10
Years
JEDEC Standard A103
I
LTH
1
Latch Up
100 + IDD
mA
JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12 : AC OPERATING CHARACTERISTICS T
A=
0~70
o
C
Normal 33MHz Fast 50 MHz
Fast 100 MHz
VDD=2.7~3.6V VDD=2.7~3.6V VDD=3.0~3.6V
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
F
CLK
Serial Clock Frequency
33
50
100
MHz
T
SCKH
Serial Clock High Time
13
9
5
ns
T
SCKL
Serial Clock Low Time
13
9
5
ns
T
CES
1
CE Active Setup Time
5
5
5
ns
T
CEH
1
CE Active Hold Time
5
5
5
ns
T
CHS
1
CE Not Active Setup Time
5
5
5
ns
T
CHH
1
CE Not Active Hold Time
5
5
5
ns
T
CPH
CE High Time
100
100
100
ns
T
CHZ
CE High to High-Z Output
9
9
9
ns
T
CLZ
SCK Low to Low-Z Output
0
0
0
ns
T
DS
Data In Setup Time
3
3
3
ns
T
DH
Data In Hold Time
3
3
3
ns
T
HLS
HOLD Low Setup Time
5
5
5
ns
T
HHS
HOLD High Setup Time
5
5
5
ns
T
HLH
HOLD Low Hold Time
5
5
5
ns
T
HHH
HOLD High Hold Time
5
5
5
ns
T
HZ
HOLD Low to High-Z Output
9
9
9
ns
T
LZ
HOLD High to Low-Z Output
9
9
9
ns
T
OH
Output Hold from SCK Change
0
0
0
ns
T
V
Output Valid from SCK
12
8
7
ns
1. Relative to SCK.
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