參數(shù)資料
型號: F25L004A-50PG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: PROM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 512K X 8 FLASH 3V PROM, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁數(shù): 17/32頁
文件大?。?/td> 393K
代理商: F25L004A-50PG
ES MT
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A
Chip-Erase instruction will be ignored if any of the memory area
is protected. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE must remain active
low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command,
F25L004A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
17/32
Publication Date
:
Apr. 2007
60H or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the software status
register or wait T
CE
for the completion of the internal self-timed
Chip-Erase cycle.
See Figure 11 for the Chip-Erase sequence.
FIGURE 11 : CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and
Read-Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE
See Figure 12 for the RDSR instruction sequence.
remain
low
until
the
status
data
is
read.
Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE
CE
SCK
SI
0
1
2
3
4
5
6
7
8
9
Bit7
MSB
MSB
HIGH IMPENANCE
SO
05
MODE3
MODE1
10
11
12
13
14
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Status
Register Out
CE
SCK
SI
0 1 2 3 4 5 6 7
MSB
HIGH IMPENANCE
SO
60 orC7
MODE3
MODE0
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