參數(shù)資料
型號(hào)： F25L004A-50DG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 512K X 8 FLASH 3V PROM, PDIP8
封裝： 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 393K
代理商： F25L004A-50DG
ES MT
Hold Operation
F25L004A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
7/32
Publication Date
:
Apr. 2007
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be V
IL
or V
IH
.
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory
remains
in
the
Hold
communication with the device, HOLD must be driven active
condition.
To
resume
high, and CE must be driven active low. See Figure 18 for Hold
timing.
Active
Hold
Active
Hold
Active
HOLD
SCK
Figure 1 : HOLD CONDITION WAVEFORM
Write Protection
F25L004A provides software Write protection.
The Write Protect pin (
WP
) enables or disables the lockdown
function of the status register. The Block-Protection bits (BP1,
BP0, and BPL) in the status register provide Write protection to
the memory array and the status register. See Table 5 for
Block-Protection description.
Write Protect Pin (
WP
)
The Write Protect (
WP
) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When
WP
is driven low,
the execution of the Write-Status-Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 3). When
WP
is high, the lock-down function of the BPL bit is disabled.
TABLE3: CONDITIONS TO EXECUTE
WRITE-STATUS- REGISTER (WRSR)
INSTRUCTION
WP
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
相關(guān)PDF資料
PDF描述
F25L004A-50PAG 4 Mbit Uniform Sector, Serial Flash Memory
HL1A100KR ALUMINIUM ELECTROLYTIC CAPACITOR
HL1A100KT ALUMINIUM ELECTROLYTIC CAPACITOR
HL1A100LC ALUMINIUM ELECTROLYTIC CAPACITOR
HL1A100LR ALUMINIUM ELECTROLYTIC CAPACITOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
F25L004A-50DIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:3V Only 4 Mbit Serial Flash Memory Operation Temperature Condition -40°C ~85°C
F25L004A-50PAG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:3V Only 4 Mbit Serial Flash Memory
F25L004A-50PAIG 制造商:ELITE SEMICONDUCTOR 功能描述:FLASH 4MB 3V SPI 50MHZ SOIC8
F25L004A-50PG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4Mbit (512Kx8) 3V Only Serial Flash Memory
F25L004A-50PIG 制造商:ELITE SEMICONDUCTOR 功能描述:FLASH 4MB 3V SPI 50MHZ SOIC8
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*