參數(shù)資料
型號： EVAL-ADV7611EB2Z
廠商： Analog Devices Inc
文件頁數(shù)： 4/16頁
文件大小： 0K
描述： BOARD EVALUATION FOR ADV7611
標準包裝： 1
系列： Advantiv®
主要目的： 視頻，HDMI 接收器
嵌入式： 是，MCU，ARM7
已用 IC / 零件： ADV7611
已供物品： 板
ADV7611
Data Sheet
Rev. D | Page 12 of 16
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7611 is highly flexible. The pixel
output bus can support up to 24-bit 4:4:4 YCrCb. The pixel data
supports both single and double data rates modes. In SDR mode, a
16-/24-bit 4:2:2 or 24-bit 4:4:4 output is possible. In DDR mode1,
the pixel output port can be configured in an 8-/12-bit 4:2:2 YCrCb
or 24-bit 4:4:4 RGB.
Bus rotation is supported. Table 5 and Table 6 outline the different
output formats that are supported. All output modes are controlled
via I2C.
1
DDR mode is only supported only up to 50 MHz (an equivalent to data rate
clocked 100 MHz clock in SDR mode).
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include:
8-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD output signals
16-/24-bit YCrCb with embedded time codes and/or HS
and VS/FIELD pin timing
24-bit YCrCb/RGB with embedded time codes and/or HS
and VS/FIELD pin timing
DDR 8-/12-bit 4:2:2 YCrCb
DDR 24-bit 4:4:4 RGB
Table 5. SDR 4:2:2 and 4:4:4 Output Modes
SDR 4:2:2
SDR 4:4:4
OP_FORMAT_SEL[7:0]
0x01
0x0A1
0x80
0x8A
0x40
Pixel Output
8-Bit SDR
ITU-R BT.656
Mode 0
12-Bit SDR
ITU-R BT.656
Mode 2
16-Bit SDR
ITU-R BT.656 4:2:2
Mode 0
24-Bit SDR
ITU-R BT.656 4:2:2
Mode 2
24-Bit SDR 4:4:4
Mode 0
P23
High-Z
Y3, Cb3, Cr3
High-Z
Y3
R7
P22
High-Z
Y2, Cb2, Cr2
High-Z
Y2
R6
P21
High-Z
Y1, Cb1, Cr1
High-Z
Y1
R5
P20
High-Z
Y0, Cb0, Cr0
High-Z
Y0
R4
P19
High-Z
Cb3, Cr3
R3
P18
High-Z
Cb2, Cr2
R2
P17
High-Z
Cb1, Cr1
R1
P16
High-Z
Cb0, Cr0
R0
P15
Y7, Cb7, Cr7
Y11, Cb11, Cr11
Y7
Y11
G7
P14
Y6, Cb6, Cr6
Y10, Cb10, Cr10
Y6
Y10
G6
P13
Y5, Cb5, Cr5
Y9, Cb9, Cr9
Y5
Y9
G5
P12
Y4, Cb4, Cr4
Y8, Cb8, Cr8
Y4
Y8
G4
P11
Y3, Cb3, Cr3
Y7, Cb7, Cr7
Y3
Y7
G3
P10
Y2, Cb2, Cr2
Y6, Cb6, Cr6
Y2
Y6
G2
P9
Y1, Cb1, Cr1
Y5, Cb5, Cr5
Y1
Y5
G1
P8
Y0, Cb0, Cr0
Y4, Cb4, Cr4
Y0
Y4
G0
P7
High-Z
Cb7, Cr7
Cb11, Cr11
B7
P6
High-Z
Cb6, Cr6
Cb10, Cr10
B6
P5
High-Z
Cb5, Cr5
Cb9, Cr9
B5
P4
High-Z
Cb4, Cr4
Cb8, Cr8
B4
P3
High-Z
Cb3, Cr3
Cb7, Cr7
B3
P2
High-Z
Cb2, Cr2
Cb6, Cr6
B2
P1
High-Z
Cb1, Cr1
Cb5, Cr5
B1
P0
High-Z
Cb0, Cr0
Cb4, Cr4
B0
1
Modes 0x00 and 0x0A require additional writes to IO Map Register 0x19[7:6] = 2’b11 and IO Map Register 0x33[6] = 1
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