參數(shù)資料
型號(hào)： EVAL-ADF4350EB2Z
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： EVALUATION BOARD 2 FOR ADF4350
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4350
主要屬性： 帶 VCO 的單路分?jǐn)?shù)-N 和整數(shù)-N PLL
次要屬性： USB 接口
已供物品： 板，纜線，CD
ADF4350
Rev. A | Page 20 of 32
REGISTER 3
Control Bits
With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed.
Figure 27 shows the input data format for programming this
register.
CSR Enable
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase fre-
quency detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge pump current setting must also
be set to a minimum. See the Cycle Slip Reduction for Faster
Lock Times section for more information.
Clock Divider Mode
Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync
or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0
disables the clock divider. See Figure 27.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of PHASE resync. See the Phase Resync section for
more information. It also sets the timeout counter for fast lock.
See the Fast-Lock Timer and Register Sequences section for
more information.
REGISTER 4
Control Bits
With Bits [C3:C1] set to 1, 0, 0, Register 4 is programmed.
Figure 28 shows the input data format for programming this
register.
Feedback Select
DB23 selects the feedback from the VCO output to the
N counter. When set to 1, the signal is taken from the VCO
directly. When set to 0, it is taken from the output of the output
dividers. The dividers enable covering of the wide frequency band
(137.5 MHz to 4.4 GHz). When the divider is enabled and the
feedback signal is taken from the output, the RF output signals
of two separately configured PLLs are in phase. This is useful in
some applications where the positive interference of signals is
required to increase the power.
Divider Select
Bits [DB22:DB20] select the value of the output divider (see
Band Select Clock Divider Value
Bits [DB19:DB12] set a divider for the band select logic
clock input. The output of the R counter, is by default, the
value used to clock the band select logic, but, if this value is
too high (>125 kHz), a divider can be switched on to divide
the R counter output to a smaller value (see Figure 28).
VCO Power-Down
DB11 powers the VCO down or up depending on the chosen value.
Mute Till Lock Detect
If DB10 is set to 1, the supply current to the RF output stage is shut
down until the part achieves lock as measured by the digital lock
detect circuitry.
AUX Output Select
DB9 sets the auxiliary RF output. The selection can be either
the output of the RF dividers or fundamental VCO frequency.
AUX Output Enable
DB8 enables or disables auxiliary RF output, depending on the
chosen value.
AUX Output Power
Bits [DB7:DB6] set the value of the auxiliary RF output power
level (see Figure 28).
RF Output Enable
DB5 enables or disables primary RF output, depending on the
chosen value.
Output Power
Bits [DB4:DB3] set the value of the primary RF output power
level (see Figure 28).
REGISTER 5
Control Bits
With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.
Figure 29 shows the input data form for programming this
register.
Lock Detect Pin Operation
Bits [DB23:DB22] set the operation of the lock detect pin (see
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