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參數(shù)資料
| 型號： | EVAL-ADF4007EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4007EB1 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4007 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 7.5GHz |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4007BCPZ-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP ADF4007BCPZ-RL7-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP ADF4007BCPZ-RL-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| 其它名稱： | Q5364837 |
ADF4007
Data Sheet
Rev. B | Page 10 of 16
MUXOUT
The output multiplexer on the ADF4007 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M2 and M1 pins. Figure 12
shows the MUXOUT section in block diagram form.
DGND
DVDD
CONTROL
MUX
DVDD
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
MUXOUT
04537-
018
Figure 12. MUXOUT Circuit
PFD Polarity
The PFD polarity is set by the state of M2 and M1 pins as given
in the Table 5. The ability to set the polarity allows the use of VCOs
with either positive or negative tuning characteristics. For standard
VCOs with positive characteristics (output frequency increases
with increasing tuning voltage), the polarity should be set to
positive. This is accomplished by tying M2 and M1 to a logic
low state.
CP Output
The CP output state is also controlled by the state of M2 and M1. It
can be set either to active (so that the loop can be locked) or to
three-state (open the loop). The normal state is CP output active.
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