參數(shù)資料
型號: EVAL-AD7982SDZ
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大小: 0K
描述: BOARD EVAL FOR AD7982
標準包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 18
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
輸入范圍: ±VREF
在以下條件下的電源(標準): 7mW @ 1MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7982
已供物品:
Data Sheet
AD7982
Rev. B | Page 17 of 24
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 29, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7982 enters the acquisition phase and powers
down. When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 18th SCK falling edge or when
CNV goes high (whichever occurs first), SDO returns to high
impedance.
AD7982
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
06
51
3-
0
16
Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDO
D17
D16
D15
D1
D0
tDIS
SCK
123
16
17
18
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
06
51
3-
0
17
Figure 30. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
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