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| 型號： | EVAL-AD7946SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7946 |
| 標準包裝： | 1 |
| 系列： | * |
AD7946
Rev. A | Page 17 of 24
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33 and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7946
04656-032
Figure 33. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO
D13
D12
D11
D1
D0
tDIS
SCK
12
3
12
13
14
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
04656-033
Figure 34. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
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