參數(shù)資料
型號(hào)： EVAL-AD7763EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL CONTROL AD7763
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： ±3.25 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 955.5mW @ 625kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7763
已供物品： 板，CD
AD7763
Data Sheet
Rev. B | Page 16 of 32
The Share Pins SH[2:0] of all the devices sharing the serial bus
must be programmed for the correct number of devices that are
sharing the serial bus. A binary value of N 1 should be applied
to the SH[2:0] bits, where N equals the number of devices in the
chain. For example if there are 4 devices in the chain set SH[2:0]
= 011.
Using the Address Pins ADR[2:0], all devices that share the
serial bus are assigned binary addresses from 000 to 111
(depending on the number of devices in the share scheme). The
address assigned to each device must not have a value greater
than the number of devices sharing the serial bus. Thus,
ADR[2:0] ≤ SH[2:0]. This applies to all the devices that share the
serial bus. Note also that each of the devices in the share scheme
must have a different individual address.
For the device in the share scheme with an address of 000, the
SDO line comes out of three-state on the first rising edge of SCO
after the DRDY pulse and returns to three-state 5.5 ns before
the 31st SCO rising edge. For the next device sharing the serial
bus, Address 001, the SDO line comes out of three-state on the
33rd SCO rising edge (that is, the first SCO rising edge of the
next conversion output cycle). Thus, the SDO line goes into tri-
state for one SCO cycle in between data being clocked onto SDO
by two different devices that share the SDO line. This means
that a bus contention issue is avoided. This pattern of behavior
continues for the rest of the devices sharing the serial bus.
Each AD7763 device sharing the serial bus outputs its own FSO
signal.
Figure 26 shows an example of four devices sharing the same
serial bus. All the devices in the share chain shown in Figure 26
operate in decimate × 64 mode (selected by writing to Control
Register 1—Address 0x001) and use a maximum SCO signal of
40 MHz (see the Clocking the AD7763 section).
The Share Pins SH[2:0] of all the devices shown in Figure 26
are set to 011, corresponding to the four devices that are in the
share configuration. Each AD7763 is hardwired with a different
binary address ranging from 000 to 011, using the Address Pins
ADR[2:0].
The timing diagram for the share configuration shown in
Figure 26 is detailed in Figure 4. Device A outputs its 32-bit
conversion result on the SDO line during the first 32 SCO
cycles (as per the format shown in the Reading Data Using the
SPI Interface section). Device B then outputs its conversion
result during the next 32 SCO cycles, and so on for Device C
and Device D. Note the way in which the SDO line is three-
stated, separating data from each of the devices sharing the
serial bus. The provision of two framing signals, DRDY and
FSO, ensures that the AD7763 offers flexible data output
framing options, which are further enhanced by the availability
of the SDL output. The user can select the framing output that
best suits the application.
WRITING TO THE AD7763
Figure 3 shows the AD7763 write operation. The serial writing
operation is synchronous to the SCO signal. The status of the
frame sync input, FSI , is checked on the falling edge of the SCO
signal. If the FSI line is low, then the first data is latched in on
the next SCO falling edge.
AD7763
(000)
MCLK
DEVICE
ADDRESS
000
SHARED
SERIAL DATA OUTPUT
(SDO)
DEVICE
ADDRESS
001
011
ADR[2:0]
FSO
FSO A
A
SH[2:0]
MCLK
SDO
DRDY
AD7763
(001)
MCLK
ADR[2:0]
FSO
FSO B
B
SH[2:0]
SDO
DEVICE
ADDRESS
010
AD7763
(010)
MCLK
ADR[2:0]
FSO
FSO C
C
SH[2:0]
SDO
DEVICE
ADDRESS
011
AD7763
(011)
MCLK
ADR[2:0]
FSO
FSO D
D
SH[2:0]
SDO
05476-
013
Figure 26. Four AD7763 Devices Sharing the Serial Bus
The active edge of the FSI signal should be set to occur at a position
when the SCO signal is high or low and which also allows setup
and hold time from the SCO falling edge to be met. The width
of the FSI signal can be set to between 1 SCO period and 32 SCO
periods wide. A second or subsequent FSI falling edge, which
occurs before 32 SCO periods have elapsed, is ignored.
Figure 3 also shows the format for the serial data written to the
AD7763. A write operation requires 32 bits. The first 16 bits select
the device and register address for which the data written is
intended. The second 16 bits contain the data for the selected
register. When using multiple devices that share the same serial bus,
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