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| 型號： | EVAL-AD7746EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7746 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 觸摸，電容式 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 嵌入式： | 否 |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD7746 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7746ARUZ-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP AD7746ARUZ-REEL7-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP AD7746ARUZ-REEL-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP |
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AD7745/AD7746
Rev. 0 | Page 4 of 28
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Full-Scale Drift vs. Temperature
5
ppm of FS/°C
Internal reference
0.5
ppm of FS/°C
External reference
Average VIN Input Current
300
nA/V
Analog VIN Input Current Drift
±50
pA/V/°C
Power Supply Rejection
80
dB
Internal reference, VIN = VREF/2
Power Supply Rejection
90
dB
External reference, VIN = VREF/2
Normal Mode Rejection
75
dB
50 Hz ± 1%, conversion time = 122.1 ms
50
dB
60 Hz ± 1%, conversion time = 122.1 ms
Common-Mode Rejection
95
dB
VIN = 1 V
INTERNAL VOLTAGE REFERENCE
Voltage
1.169
1.17
1.171
V
TA = 25°C
Drift vs. Temperature
5
ppm/°C
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage2
0.1
2.5
VDD
V
Absolute REFIN Voltage2
GND 0.03
VDD + 0.03
V
Average REFIN Input Current
400
nA/V
Average REFIN Input Current Drift
±50
pA/V/°C
Common-Mode Rejection
80
dB
SERIAL INTERFACE LOGIC INPUTS
(SCL, SDA)
VIH Input High Voltage
2.1
V
VIL Input Low Voltage
0.8
V
Hysteresis
150
mV
Input Leakage Current (SCL)
±0.1
±1
A
OPEN-DRAIN OUTPUT (SDA)
VOL Output Low Voltage
0.4
V
ISINK =
6.0 mA
IOH Output High Leakage Current
0.1
1
A
VOUT = VDD
LOGIC OUTPUT (RDY)
VOL Output Low Voltage
0.4
V
ISINK = 1.6 mA, VDD = 5 V
VOH Output High Voltage
4.0
V
ISOURCE = 200 A, VDD = 5 V
VOL Output Low Voltage
0.4
V
ISINK = 100 A, VDD = 3 V
VOH Output High Voltage
VDD – 0.6
V
ISOURCE = 100 A, VDD = 3 V
POWER REQUIREMENTS
VDD-to-GND Voltage
4.75
5.25
V
VDD = 5 V, nominal
2.7
3.6
V
VDD = 3.3 V, nominal
IDD Current
850
A
Digital inputs equal to VDD or GND
750
A
VDD = 5 V
700
A
VDD = 3.3 V
IDD Current Power-Down Mode
0.5
2
A
Digital inputs equal to VDD or GND
1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At
different temperatures, compensation for gain drift over temperature is required.
4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger
offset can be removed using CAPDACs.
5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
6 The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can
further reduce the CIN offset or the unchanging CIN component.
7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 41, with total serial resistance <100 .
9 Full-scale error applies to both positive and negative full scale.
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