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參數(shù)資料
| 型號(hào)： | EVAL-AD7705EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 43/44頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7705 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.25 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 6.5mW @ 500SPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7705 |
| 已供物品： | 板，CD |
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AD7705/AD7706
Rev. C | Page 8 of 44
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.
Table 2. Timing Characteristics1, 2
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
400
kHz min
Master clock frequency (crystal oscillator or externally supplied)
2.5
MHz max
For specified performance
tCLKIN LO
0.4 × tCLKIN
ns min
Master clock input low time, tCLKIN = 1/fCLKIN
tCLKIN HI
0.4 × tCLKIN
ns min
Master clock input high time
t1
500 × tCLKIN
ns nom
DRDY high time
t2
100
ns min
RESET pulse width
Read Operation
t3
0
ns min
DRDY to CS setup time
t4
120
ns min
CS falling edge to SCLK rising edge setup time
t55
0
ns min
SCLK falling edge to data valid delay
80
ns max
VDD = 5 V
100
ns max
VDD = 3.0 V
t6
100
ns min
SCLK high pulse width
t7
100
ns min
SCLK low pulse width
t8
0
ns min
CS rising edge to SCLK rising edge hold time
10
ns min
Bus relinquish time after SCLK rising edge
60
ns max
VDD = 5 V
100
ns max
VDD = 3.0 V
t10
100
ns max
SCLK falling edge to DRDY high7
Write Operation
t11
120
ns min
CS falling edge to SCLK rising edge setup time
t12
30
ns min
Data valid to SCLK rising edge setup time
t13
20
ns min
Data valid to SCLK rising edge hold time
t14
100
ns min
SCLK high pulse width
t15
100
ns min
SCLK low pulse width
t16
0
ns min
CS rising edge to SCLK rising edge hold time
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 19 and Figure 20.
3 The fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw
higher current than specified, and possibly become uncalibrated.
4 The AD7705/AD7706 are production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY returns high upon completion of the first read from the device after an output update. The same data can be reread while DRDY is high, but care should be
taken that subsequent reads do not occur close to the next output update.
TO OUTPUT
PIN
50pF
ISINK (800μA AT VDD = 5V
100
μA AT V
DD = 3V)
1.6V
ISOURCE (200μA AT VDD = 5V
100mA AT VDD = 3V)
01166-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EVAL-AD7706EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7706EBZ | 功能描述:BOARD EVALUATION FOR AD7706 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7707EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR 3V/5 V, 610 V INPUT RANGE, 1 MW 3-CH 16BIT, SIG - Bulk |
| EVAL-AD7708EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7708EBZ | 功能描述:BOARD EVAL FOR AD7708 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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