t3 BUSY CS, RD CNVST SYNC SCLK SDOUT t28
參數(shù)資料
型號: EVAL-AD7671CBZ
廠商: Analog Devices Inc
文件頁數(shù): 10/24頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD7671
標準包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: ±4 REF
在以下條件下的電源(標準): 112mW @ 1MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7671
已供物品:
相關產(chǎn)品: AD7671ACPZ-ND - IC ADC 16BIT CMOS 1MSPS 48LFCSP
AD7671ACPZRL-ND - IC ADC 16BIT CMOS 1MSPS 48LFCSP
AD7671ASTZRL-ND - IC ADC 16BIT CMOS 1MSPS 48LQFP
AD7671ASTZ-ND - IC ADC 16BIT CMOS 1MSPS 48-LQFP
AD7671
–18–
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t3
t1
t17
t14
t19
t20 t21
t24
t26
t25
t27
t23
t22
t16
t15
D15
D14
D2
D1
D0
X
12
3
14
15
16
t18
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
MASTER SERIAL INTERFACE
Internal Clock
The AD7671 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held LOW. It also gener-
ates a SYNC signal to indicate to the host when the serial data is
valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during conversion. Figures 17 and 18
show the detailed timing diagrams of these two modes.
Usually, because the AD7671 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
Serial Mode when it can be used.
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
While the AD7671 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
dation of the conversion result could occur. This is particularly
important during the second half of the conversion phase because
REV. C
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