- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17039 > EVAL-AD7666CBZ (Analog Devices Inc)BOARD EVALUATION FOR AD7666 PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD7666CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7666 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 81mW @ 500kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7666 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD7666ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP AD7666ASTZ-ND - IC ADC 16BIT UNIPOLAR 48LQFP AD7666ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP AD7666ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD7666
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7666 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7666 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
While the AD7666 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7666 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
X15
X14
X
1
2
3
14
151617
18
t34
03033-0-034
EXT/INT = 1
RD
RD = 0
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
SDOUT
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
t3
t35
t36 t37
t31
t32
t16
BUSY
EXT/INT = 1
INVSCLK = 0
03033-0-035
CNVST
CS
RD = 0
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
相關PDF資料 |
PDF描述 |
|---|---|
| MLK1005S5N1S | INDUCTOR MULTILAYER 5.1NH 0402 |
| 0210490323 | CABLE JUMPER 1.25MM .051M 26POS |
| EVAL-AD7664CBZ | BOARD EVALUATION FOR AD7664 |
| 0210391035 | CABLE JUMPER 1MM .076M 33POS |
| MPC5510KIT208 | KIT DEVELOPMENT FOR MPC5 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7667CB | 制造商:Analog Devices 功能描述: |
| EVAL-AD7667CBZ | 功能描述:BOARD EVALUATION FOR AD7667 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7668CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
| EVAL-AD766XCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
| EVAL-AD7671CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
發(fā)布緊急采購，3分鐘左右您將得到回復。