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Data Sheet
AD7656/AD7657/AD7658
Rev. D | Page 9 of 32
TIMING SPECIFICATIONS
AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = 5 V to 16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external,
TA = TMIN to TMAX, unless otherwise noted.1 Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
VDRIVE < 4.75 V
VDRIVE = 4.75 V to 5.25V
PARALLEL MODE
tCONVERT
3
s typ
Conversion time, internal clock
tQUIET
150
ns min
Minimum quiet time required between bus relinquish
and start of next conversion
tACQ
550
ns min
Acquisition time
t10
25
ns min
Minimum CONVST low pulse
t1
60
ns max
CONVST high to BUSY high
tWAKE-UP
2
ms max
STBY rising edge to CONVST rising edge
25
s max
Partial power-down mode
PARALLEL WRITE OPERATION
t11
15
ns min
WR pulse width
t12
0
ns min
CS to WR setup time
t13
5
ns min
CS to WR hold time
t14
5
ns min
Data setup time before WR rising edge
t15
5
ns min
Data hold after WR rising edge
PARALLEL READ OPERATION
t2
0
ns min
BUSY to RD delay
t3
0
ns min
CS to RD setup time
t4
0
ns min
CS to RD hold time
t5
45
36
ns min
RD pulse width
t6
45
36
ns max
Data access time after RD falling edge
t7
10
ns min
Data hold time after RD rising edge
t8
12
ns max
Bus relinquish time after RD rising edge
t9
6
ns min
Minimum time between reads
SERIAL INTERFACE
fSCLK
18
MHz max
Frequency of serial read clock
t16
12
ns max
Delay from CS until SDATA three-state disabled
22
ns max
Data access time after SCLK rising edge/CS falling edge
t18
0.4 tSCLK
ns min
SCLK low pulse width
t19
0.4 tSCLK
ns min
SCLK high pulse width
t20
10
ns min
SCLK to data valid hold time after SCLK falling edge
t21
18
ns max
CS rising edge to SDATA high impedance
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
A buffer is used on the data output pins for this measurement.
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
25pF
05020-
002
Figure 2. Load Circuit for Digital Output Timing Specification