參數(shù)資料
型號(hào): EVAL-AD7655CBZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 13/28頁(yè)
文件大小: 0K
描述: BOARD EVALUATION FOR AD7655
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: 0 ~ 2 V
在以下條件下的電源(標(biāo)準(zhǔn)): 120mW @ 1MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7655
已供物品: 板,CD
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AD7655
Rev. B | Page 20 of 28
SERIAL INTERFACE
The AD7655 is configured to use the serial interface when the
SER/PAR is held high. The AD7655 outputs 32 bits of data, MSB
first, on the SDOUT pin. The order of the channels being output
is also controlled by A/B. When high, Channel A is output first;
when low, Channel B is output first. This data is synchronized
with the 32 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7655 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired, using the INVSCLK
and INVSYNC inputs, respectively. The output data is valid on
both the rising and falling edge of the data clock. In this mode,
the D7/RDC/SDIN input is used to select between reading after
conversion (RDC = low) or reading previous conversion results
during conversion (RDC = high). Figure 28 and Figure 29 show
the detailed timing diagrams of these two modes.
Usually, because the AD7655 is used with a fast throughput, the
master read during convert mode is the most recommended
serial mode when it can be used. In this mode, the serial clock
and data toggle at appropriate instants, which minimizes
potential feed through between digital activity and the critical
conversion decisions. The SYNC signal goes low after the LSB
of each channel has been output. Note that in this mode, the
SCLK period changes because the LSBs require more time to
settle, and the SCLK is derived from the SAR conversion clock.
Note that in master read after convert mode, unlike in other
modes, the BUSY signal returns low after the 32 bits of data are
pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of using this
mode is that it can accommodate slow digital hosts because the
serial clock can be slowed down by using the DIVSCLK[1:0]
inputs. Refer to Table 4 for the timing details.
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EVAL-AD7656-1CBZ 功能描述:BOARD EVAL FOR AD7656-1 RoHS:是 類(lèi)別:編程器,開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率(每秒):94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源(標(biāo)準(zhǔn)):- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,軟件
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EVAL-AD7656CB 制造商:Analog Devices 功能描述: