t1 t3
參數(shù)資料
型號(hào)： EVAL-AD7650CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7650
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 570k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 150mW @ 570kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7650
已供物品： 板
相關(guān)產(chǎn)品： AD7650ACPZ-ND - IC ADC 16BIT CMOS 5V 48LFCSP
AD7650ASTZ-ND - IC ADC 16BIT 570KSPS 48LQFP
AD7650ASTZRL-ND - IC ADC 16BIT CMOS 5V 48LQFP
AD7650ACPZRL-ND - IC ADC 16BIT CMOS 5V 48LFCSP
REV. 0
AD7650
–14–
PREVIOUS
CONVERSION
t1
t3
t12
t13
t4
CS = 0
CNVST,
RD
BUSY
DATA
BUS
Figure 12. Slave Parallel Data Timing for Reading
(Read During Convert)
SERIAL INTERFACE
The AD7650 is configured to use the serial interface when the
SER/
PAR is held high. The AD7650 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on SCLK pin. The output data is
valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7650 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held low. The AD7650
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. Depending on RDC/SDIN input, the
data can be read after each conversion or during the following
conversion. Figure 13 and Figure 14 show the detailed timing
diagrams of these two modes.
PARALLEL INTERFACE
The AD7650 is configured to use the parallel interface when the
SER/
PAR is held low. The data can be read either after each
conversion, which is during the next acquisition phase, or dur-
ing the following conversion as shown, respectively, in Figure 11
and Figure 12. When the data is read during the conversion,
however, it is recommended that it is read only during the first
half of the conversion phase. That avoids any potential feed-
through between voltage transients on the digital interface and
the most critical analog conversion circuitry.
CURRENT
CONVERSION
BUSY
DATA
BUS
CS
RD
t12
t13
Figure 11. Slave Parallel Data Timing for Reading
(Read After Convert)
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
Figure 13. Master Serial Data Timing for Reading (Read After Convert)
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