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參數(shù)資料
| 型號： | EVAL-AD7641CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7641 |
| 產(chǎn)品培訓模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標準）： | 2MSPS 帶內部基準時為 75mW |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7641 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD7641BSTZRL-ND - IC ADC 18BIT 2MSPS SAR 48-LQFP AD7641BCPZRL-ND - IC ADC 18BIT 2MSPS SAR 48-LFCSP AD7641BSTZ-ND - IC ADC 18BIT 2MSPS SAR 48-LQFP AD7641BCPZ-ND - IC ADC 18BIT 2MSPS SAR 48-LFCSP |
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AD7641
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
An example of the concatenation of two devices is shown in
Figure 37. Simultaneous sampling is possible by using a
common
The AD7641 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.
INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive.
0
47
61
-03
8
SCLK
SDOUT
RDC/SDIN
AD7641
#1
(DOWNSTREAM)
AD7641
#2
(UPSTREAM)
BUSY
OUT
BUSY
DATA
OUT
SCLK
RDC/SDIN
SDOUT
SCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
diagrams of these methods.
While the AD7641 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7641 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
Figure 37.Two AD7641 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 39 shows the detailed timing diagrams of this method.
During a conversion, while
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 38 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the conversion result can be read while both CS
and RD are low. Data is shifted out MSB first with 18 clock
pulses and is valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.
Finally, in this mode only, the AD7641 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
CS
RD
and
are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 60 MHz when normal mode is
used, or 80 MHz when warp mode is used) is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
However, this is not recommended when using the fastest
throughput of any mode because the acquisition time, t8, is
only 115 ns.
If the maximum throughput is not used, thus allowing more
acquisition time, then the use of a slower clock speed can be
used to read the data.
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| EVAL-AD7641EDZ | 功能描述:BOARD EVAL FOR AD7641 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:* 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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| EVAL-AD7643CBZ | 功能描述:BOARD EVALUATION FOR AD7643 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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