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參數(shù)資料
| 型號： | EVAL-AD7484CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7484 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標準）： | 90mW @ 3MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7484 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7484BSTZ-ND - IC ADC 14BIT SAR 3MSPS 48-LQFP |
AD7484
Rev. C | Page 15 of 20
000...000
0V
ADC
CO
DE
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
0.5LSB
–OFFSET
+VREF – 1.5LSB
–OFFSET
1LSB = VREF/16384
02642-
022
Figure 22. Transfer Characteristic with Negative Offset
Table 5 shows the expected ADC result for a given analog input
voltage with different offset values and with CLIP tied to logic
high. The combined advantages of the offset and overrange
features of the AD7484 are shown in Table 6. Table 6 shows the
same range of analog input and offset values as Table 5 but with
the clipping feature disabled.
Table 5. Clipping Enabled (CLIP = 1)
ADC DATA, D[0:13]
Offset VIN
512
0
+1024
D14
200 mV
0
1 1 1
156.3 mV
0
1 1 0
0 V
0
1024
1 0 0
+78.2 mV
0
512
1536
0 0 0
+2.3434 V
14,846
15,358
16,383
0 0 0
+2.5 V
15,871
16,383
0 0 1
+2.5782 V
16,383
0 1 1
+2.7 V
16,383
1 1 1
Table 6. Clipping Disabled (CLIP = 0)
ADC DATA, D[0:14]
Offset VIN
512
0
+1024
200 mV
1823
1311
287
156.3 mV
1536
1024
0
0 V
512
0
1024
+78.2 mV
0
512
1536
+2.3434 V
14,846
15,358
16,382
+2.5 V
15,872
16,384
17,408
+2.5782 V
16,384
16,896
17,920
+2.7 V
17,183
17,695
18,719
If the CLIP input is at logic low, the overrange indicator is
disabled and the AD7484 can achieve output codes outside the
nominal 14-bit range of 0 to 16,383 (see Table 6). D14 acts as an
indicator that the ADC is outside this nominal range. If the
ADC is outside this nominal range on the negative side, the
ADC outputs a twos complement code and if the ADC is outside
the range on the positive side, the ADC outputs a straight binary
code as normal. If D14 is Logic 1, D13 indicates if the ADC is
out of range on the positive or negative side. If DB13 is Logic 1,
the ADC is outside the nominal range on the negative side and
the output code is a 15-bit twos complement number (a negative
number). If D13 is Logic 0, the ADC is outside the nominal
range on the positive side and the output code is a 15-bit
straight binary code (see Table 7).
Table 7. DB14, DB13 Decoding, CLIP = 0
DB14
DB13
Output Coding
0
Straight binary–inside nominal range
0
1
Straight binary–inside nominal range
1
0
Straight binary–outside nominal range
1
Twos complement–outside nominal range
Values from 1310 to +1310 can be written to the offset register.
These values correspond to an offset of ±200 mV. A write to the
offset register is performed by writing a 13-bit word to the part,
as detailed in the Parallel Interface section. The 12 LSBs of the
15-bit word contain the offset value, whereas the 3 MSBs must
be set to 0. Failure to write 0s to the 3 MSBs may result in the
incorrect operation of the device.
PARALLEL INTERFACE
The AD7484 features two parallel interfacing modes. These
modes are selected by the mode pins (see Table 8).
Table 8. Operating Modes
Operating Mode
Mode 2
Mode 1
Do Not Use
0
Parallel Mode 1
0
1
Parallel Mode 2
1
0
Do Not Use
1
In Parallel Mode 1, the data in the output register is updated on
the rising edge of BUSY at the end of a conversion and is available
for reading almost immediately afterwards. Using this mode,
throughput rates of up to 2.5 MSPS can be achieved. This mode
is to be used if the conversion data is required immediately after
the conversion is completed. An example where this may be of use
is if the AD7484 is operating at much lower throughput rates in
conjunction with the nap mode (for power saving reasons), and
the input signal is being compared with set limits within the
DSP or other controller. If the limits are exceeded, the ADC is
brought immediately into full power operation and commences
sampling at full speed. Figure 31 shows a timing diagram for the
AD7484 operating in Parallel Mode 1 with both CS and
In Parallel Mode 2, the data in the output register is not updated
until the next falling edge of
RD
tied low.
CONVST. This mode can be used
where a single sample delay is not vital to the system operation,
and conversion speeds of greater than 2.5 MSPS are desired. For
example, this may occur in a system where a large amount of
samples are taken at high speed before an FFT is performed for
frequency analysis of the input signal. Figure 32 shows a timing
diagram for the AD7484 operating in Parallel Mode 2 with both
CS and RD tied low.
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