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參數(shù)資料
| 型號： | EVAL-AD7466CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7466 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 3.6 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 0.9mW @ 100kSPS，3 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7466 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7466BRTZREEL7DKR-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRTZ-R2-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-REEL7-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRTZ-REEL-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-REEL-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRTZREEL7CT-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRTZREEL7TR-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRT-R2CT-ND - IC ADC 12BIT 1.6V LP SOT23-6 |
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AD7466/AD7467/AD7468
Rev. C | Page 12 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
6
5
4
1
2
3
VDD
GND
VIN
SDATA
SCLK
TOP VIEW
(Not to Scale)
AD7466/
AD7467/
AD7468
02643-005
CS
Figure 4. SOT-23 Pin Configuration
8
7
6
5
1
2
3
4
NC = NO CONNECT
SDATA
GND
VIN
NC
SCLK
VDD
TOP VIEW
(Not to Scale)
AD7466/
AD7467/
AD7468
02643-006
CS
Figure 5. MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOT-23
MSOP
Mnemonic
Description
6
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
devices and frames the serial data transfer.
1
8
VDD
Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V.
2
7
GND
Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should
be referred to this GND voltage.
3
6
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
5
2
SDATA
Data Out. Logic output. The conversion result from the AD7466/AD7467/AD7468 is provided on this
output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data
stream from the AD7466 consists of four leading zeros followed by the 12 bits of conversion data,
provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10
bits of conversion data, provided MSB first. The data stream from the AD7468 consists of four leading
zeros followed by the 8 bits of conversion data, provided MSB first.
4
3
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the parts. This clock
input is also used as the clock source for the conversion process of the parts.
4, 5
NC
No Connect.
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