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參數(shù)資料
| 型號： | EVAL-AD7450CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7450 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±VREF/2 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 9mW @ 1MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7450 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7450BRZ-ND - IC ADC 12BIT DIFF IN 1MSPS 8SOIC AD7450BRMZ-ND - IC ADC 12BIT DIFF IN 1MSPS 8MSOP AD7450ARMZ-ND - IC ADC 12BIT DIFF IN 1MSPS 8MSOP AD7450ABRMZ-ND - IC ADC 12BIT DIFF IN 1MSPS 8MSOP AD7450ARZ-REEL7-ND - IC ADC 12BIT DIFF IN 1MSPS 8SOIC AD7450ARMZ-REEL7-ND - IC ADC 12BIT DIFF IN 1MSPS 8MSOP AD7450ABRTZ-REEL7TR-ND - IC ADC 12BIT DIFF 1MSPS SOT23-8 AD7450ARZ-REEL-ND - IC ADC 12BIT DIFF IN 1MSPS 8SOIC AD7450ARZ-ND - IC ADC 12BIT DIFF-IN 1MSPS 8SOIC AD7450ABRT-R2CT-ND - IC ADC 12BIT W/DIFF INP SOT-23-8 更多... |
–4–
AD7450
Limit at TMIN, TMAX
Parameter
3 V
5 V
Unit
Description
fSCLK
4
50
kHz min
15
18
MHz max
tCONVERT
16
tSCLK
16
tSCLK
tSCLK = 1/fSCLK
1.07
0.88
s max
SCLK = 15 MHz, 18 MHz
tQUIET
25
ns min
Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of
CS
t1
10
ns min
Minimum
CS Pulsewidth
t2
10
ns min
CS Falling Edge to SCLK Falling Edge Setup Time
t3
5
20
ns max
Delay from
CS Falling Edge until SDATA Three-State Disabled
t4
5
40
ns max
Data Access Time after SCLK Falling Edge
t5
0.4 tSCLK
ns min
SCLK High Pulsewidth
t6
0.4 tSCLK
ns min
SCLK Low Pulsewidth
t7
10
ns min
SCLK Edge to Data Valid Hold Time
t8
6
10
ns min
SCLK Falling Edge to SDATA Three-State Enabled
35
ns max
SCLK Falling Edge to SDATA Three-State Enabled
tPOWER-UP
7
11
s max
Power-Up Time from Full Power-Down
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
2See Figure 1 and the Serial Interface section.
3Common-mode voltage.
4Mark/space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD = 5 V, and the time for an output to cross
0.4 V or 2.0 V for VDD = 3 V.
6t
8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7See Power-Up Time section.
Specifications subject to change without notice.
1
2
345
13
16
15
14
00
DB11
DB10
DB2
DB1
DB0
t
2
4 LEADING ZEROS
t
8
t
QUIET
t
CONVERT
CS
SCLK
SDATA
t
6
t
7
t
4
t
5
t
3
t
1
THREE-STATE
Figure 1. Serial Interface Timing Diagram
TIMING SPECIFICATIONS1, 2 (V
DD = 2.7 V to 3.3 V, fSCLK = 15 MHz, fS = 833 kSPS, VREF = 1.25 V; VDD = 4.75 V to 5.25 V,
fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM
3 = V
REF; TA = TMIN to TMAX, unless otherwise noted.)
Rev. A
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