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參數(shù)資料
| 型號(hào)： | EVAL-AD7401AEDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7401 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | iCoupler® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±320 mV |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 105mW @ 20MSPS |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7401A |
| 已供物品： | 板 |
AD7401A
Rev. C | Page 14 of 20
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7401A isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average single-bit data from the modulators
is directly proportional to the input signal. Figure 23 shows a
typical application circuit where the AD7401A is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
ANALOG INPUT
The differential analog input of the AD7401A is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is external
on the AD7401A. The analog input signal is continuously
sampled by the modulator and compared to an internal
voltage reference. A digital stream that accurately represents
the analog input over time appears at the output of the
converter (see Figure 21).
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
07
332-
021
Figure 21. Analog Input vs. Modulator Output
A differential signal of 0 V results (ideally) in a stream of alter-
nating 1s and 0s at the MDAT output pin. This output is high
50% of the time and low 50% of the time. A differential input of
200 mV produces a stream of 1s and 0s that are high 81.25% of
the time (for a +250 mV input, the output stream is high 89.06% of
the time). A differential input of 200 mV produces a stream of
1s and 0s that are high 18.75% of the time (for a 250 mV
input, the output stream is high 10.94% of the time).
A differential input of 320 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7401A, and
200 mV is the specified full-scale range, as shown in Table 9.
Table 9. Analog Input Range
Analog Input
Voltage Input
Full-Scale Range
+640 mV
Positive Full Scale
+320 mV
Positive Typical Input Range
+250 mV
Positive Specified Input Range
+200 mV
Zero
0 mV
Negative Specified Input Range
200 mV
Negative Typical Input Range
250 mV
Negative Full Scale
320 mV
To reconstruct the original information, this output needs to be
digitally filtered and decimated. A sinc3 filter is recommended
because this is one order higher than that of the AD7401A modu-
lator. If a 256 decimation rate is used, the resulting 16-bit word
rate is 62.5 kHz, assuming a 16 MHz external clock frequency.
Figure 22 shows the transfer function of the AD7401A relative
to the 16-bit output.
65535
53248
SPECIFIED RANGE
ANALOG INPUT
ADC
C
O
DE
12288
–320mV
–200mV
+200mV +320mV
0
07
33
2-
0
22
Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic
Σ-
MOD/
ENCODER
INPUT
CURRENT
NONISOLATED
5V/3V
ISOLATED
5V
VDD1
RSHUNT
VIN+
VIN–
GND1
VDD
GND
VDD2
MDAT
SINC3 FILTER*
AD7401A
MCLKIN
SDAT
CS
SCLK
MCLK
GND2
DECODER
+
ENCODER
07
33
2-
02
3
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP.
Figure 23. Typical Application Circuit
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