參數(shù)資料
型號(hào)： EVAL-AD5669REBRZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5669 TSSOP
標(biāo)準(zhǔn)包裝： 1
系列： denseDAC
DAC 的數(shù)量： 8
位數(shù)： 16
數(shù)據(jù)接口： I²C，串行
設(shè)置時(shí)間： 2.5µs
DAC 型： 電壓
工作溫度： -40°C ~ 105°C
已供物品： 板
已用 IC / 零件： AD5669
Data Sheet
AD5629R/AD5669R
Rev. D | Page 25 of 32
POWER-DOWN MODES
The AD5629R/AD5669R contain four separate modes of
operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for
the contents of the input shift register during power-down/power-
up operation.
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 A at
5 V (0.2 A at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 k or a 100 k resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 55.
RESISTOR
NETWORK
VOUT
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
08819-
051
Figure 55. Output Stage During Power-Down
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry is shut down
when the power-down mode is activated. The internal reference
is powered down only when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down. The time to exit power-down is typically 4 s
for VDD = 5 V and for VDD = 3 V.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC low) or to the value in the
DAC register before powering down (LDAC high).
CLEAR CODE REGISTER
The AD5629R/AD5669R have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge
sensitive. Bringing the CLR line low clears the contents of the
input register and the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits, Bit
DB1 and Bit DB0, in the CLR control register (see Table 15).
The default setting clears the outputs to 0 V. Command 0101
is reserved for loading the clear code register (see Table 8).
The part exits clear code mode at the end of the next valid write
to the part. If CLR is activated during a write sequence, the write
is aborted.
The CLR pulse activation time (the falling edge of CLR to when
the output starts to change) is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing CLR for the output to start changing (see Figure 44).
See Table 14 for the contents of the input shift register during
the loading clear code register operation.
Table 10. Internal Reference Register
Internal REF Register (DB0)
Action
0
Reference off (default)
1
Reference on
Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
DB0
1
0
X
1/0
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Internal REF on/off
相關(guān)PDF資料
PDF描述
GBM24DRYS CONN EDGECARD 48POS DIP .156 SLD
RBA10DTBI CONN EDGECARD 20POS R/A .125 SLD
DC1190A-A BOARD SAR ADC LTC2366
V24C48E150BF CONVERTER MOD DC/DC 48V 150W
0210390935 CABLE JUMPER 1MM .203M 23POS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5669RSDZ 功能描述:BOARD EVAL FOR AD5669 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:denseDAC 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5680EB 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V 18-Bit nanoDAC in a SOT-23
EVAL-AD5680EBZ 功能描述:BOARD EVAL FOR AD5680 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5684RSDZ 功能描述:BOARD EVAL FOR AD5684R RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5686RSDZ 功能描述:BOARD EVAL FOR AD5686R RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*