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參數(shù)資料
| 型號： | EVAL-AD5532HSEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5532HS |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 32 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1.1M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 10µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5532HS |
| 相關(guān)產(chǎn)品： | AD5532HSABCZ-ND - IC DAC 14BIT 32CH HS 74-CSPBGA AD5532BBCZ-1-ND - IC DAC 14BIT 32CH BIPO 74-CSPBGA AD5532ABCZ-5-ND - IC DAC 14BIT 32CH BIPO 74-CSPBGA AD5532ABCZ-3-ND - IC DAC 14BIT 32CH BIPO 74-CSPBGA AD5532ABCZ-2-ND - IC DAC 14BIT 32CH BIPO 74-CSPBGA AD5532ABCZ-1REEL-ND - IC DAC 14BIT 32CH BIPO 74-CSPBGA AD5532ABCZ-1-ND - IC DAC 14BIT VOUT 32CH 74-CSPBGA AD5532HSABC-ND - IC DAC 14BIT 32CH 74-CSPBGA AD5532ABC-5-ND - IC DAC 14BIT 32CH 74-CSPBGA AD5532ABC-3-ND - IC DAC 14BIT 32CH 74-CSPBGA 更多... |
REV. 0
–3–
AD5532HS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
1, 2
A Version
3
Unit
Conditions/Comments
Output Voltage Settling Time
4
10
s max
100 pF, 5 k
Load; Full-Scale Change
Slew Rate
0.85
V/
s typ
Digital-to-Analog Glitch Impulse
1
nV-s typ
1 LSB Change around Major Carry
Digital Crosstalk
5
nV-s typ
Analog Crosstalk
1
nV-s typ
Digital Feedthrough
0.2
nV-s typ
Output Noise Spectral Density @ 1 kHz
170
nV/
√Hz typ
NOTES
1See Terminology
2Guaranteed by design and characterization, not production tested
3B Version: Industrial temperature range –40
°C to +85°C.
4Timed from the end of a write sequence.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Limit at TMIN, TMAX
Parameter
1, 2, 3
(A Version)
Unit
Conditions/Comments
fUPDATE
1.1
MHz max
Channel Update Rate
fCLKIN
30
MHz max
SCLK Frequency
t1
13
ns min
SCLK High Pulsewidth
t2
13
ns min
SCLK Low Pulsewidth
t3
15
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time
t4
50
ns min
SYNC Low Time
t5
10
ns min
SYNC High Time
t6
10
ns min
DIN Setup Time
t7
5
ns min
DIN Hold Time
t8
280
ns min
19th SCLK Falling Edge to SYNC Falling Edge for Next Write
t9
20
ns min
RESET Pulsewidth
NOTES
1See Timing Diagrams in Figure 1.
2Guaranteed by design and characterization, not production tested.
3All input signals are specified with t
R = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
AC CHARACTERISTICS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DAC_GND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
1
23
45
t1
t2
t3
t4
LSB
t6
t7
16
17
18
19
MSB
SCLK
SYNC
DIN
t8
1
t9
RESET
t5
Figure 1. Serial Interface Timing Diagram
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