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| 型號： | EVAL-AD5242EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5242 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5242 |
| 已供物品： | 板 |
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AD5241/AD5242
Rev. C | Page 13 of 20
The typical distribution of the nominal resistance RAB from
channel to channel matches within ±1% for AD5242. Device-
to-device matching is process lot dependent, and it is possible to
have ±30% variation. Because the resistance element is processed in
thin film technology, the change in RAB with temperature has no
more than a 30 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input
voltage at A-to-B. Unlike the polarity of VDD /VSS, which must
be positive, voltage across terminal A to terminal B, terminal W
to terminal A, and terminal W to terminal B can be at either
polarity provided that VSS is powered by a negative supply.
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less
than 5 V. Each LSB of voltage is equal to the voltage applied across
Terminal AB divided by the 256 positions of the potentiometer
divider. Because AD5241/AD5242 can be supplied by dual
supplies, the general equation defining the output voltage at VW
with respect to ground for any valid input voltage applied to
Terminal A and Terminal B is
()
B
A
W
V
D
V
D
V
256
+
=
(3)
which can be simplified to
()
B
AB
W
V
D
V
+
=
256
(4)
where D is the decimal equivalent of the binary code between 0
to 255 that is loaded in the 8-bit RDAC register.
For a more accurate calculation, including the effects of wiper
resistance, VW can be found as
()
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
+
=
(5)
where RWB(D) and RWA(D) can be obtained from Equation 1 and
Equation 2.
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent on the ratio of the internal
resistors, RWA and RWB, and not the absolute values; therefore,
the temperature drift reduces to 5 ppm/°C.
DIGITAL INTERFACE
2-Wire Serial Bus
The AD5241/AD5242 are controlled via an I2C-compatible
serial bus. The RDACs are connected to this bus as slave devices.
AD5242 is a slave address byte. It has a 7-bit slave address and
an R/W bit. The five MSBs are 01011 and the following two bits
are determined by the state of the AD0 and AD1 pins of the
device. AD0 and AD1 allow users to use up to four of these
devices on one bus.
The 2-wire, I2C serial bus protocol operates as follows:
1.
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 4). The following
byte is the Frame 1, slave address byte, which consists of the
7-bit slave address followed by an R/W bit (this bit determines
whether data is read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is the acknowledge bit). At this stage,
all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master reads from the
slave device. If the R/W bit is low, the master writes to the
slave device.
2.
A write operation contains an extra instruction byte more
than the read operation. The Frame 2 instruction byte in
write mode follows the slave address byte. The MSB of the
instruction byte labeled A/B is the RDAC subaddress select. A
low selects RDAC1 and a high selects RDAC2 for the dual-
channel AD5242. Set A/B to low for the AD5241. The
second MSB, RS, is the midscale reset. A logic high of this
bit moves the wiper of a selected RDAC to the center tap
where RWA = RWB. The third MSB, SD, is a shutdown bit. A
logic high on SD causes the RDAC to open circuit at
Terminal A while shorting the wiper to Terminal B. This
operation yields almost a 0 Ω rheostat mode or 0 V in
potentiometer mode. This SD bit serves the same function
as the SHDN pin except that the SHDN pin reacts to active
low. The following two bits are O2 and O1. They are extra
programmable logic outputs that users can use to drive
other digital loads, logic gates, LED drivers, analog switches,
and the like. The three LSBs are don’t care (see
).
3.
After acknowledging the instruction byte, the last byte in
write mode is the, Frame 3 data byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (eight
data bits followed by an acknowledge bit). The transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (see Figure 4).
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