- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1920 > ET80960JT10016 (Intel)IC MPU I960JT 3V 100MHZ 132-QFP PDF資料下載
參數(shù)資料
| 型號： | ET80960JT10016 |
| 廠商： | Intel |
| 文件頁數(shù)： | 40/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU I960JT 3V 100MHZ 132-QFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 處理器類型： | i960 |
| 特點(diǎn)： | 后綴 JT，32 位 16K 高速緩沖 |
| 速度： | 100MHz |
| 電壓： | 3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-QFP |
| 供應(yīng)商設(shè)備封裝： | 132-QFP |
| 包裝： | 托盤 |
| 其它名稱： | 864017 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Datasheet
45
4.7.1
A.C. Test Conditions and Derating Curves
The A.C. Specifications in Section 4.7, “A.C. Specifications” are tested with the 50 pF load
indicated in Figure 10.
Refer to the following sections for the specified derating curves:
Table 23. Note Definitions for Table 22, 80960Jx AC Characteristics
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than IOL. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees
recognition at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be asserted
for a minimum of two CLKIN periods to ensure recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11. Worst-case TOV condition occurs on I/O pins when pins transition from a floating high input to driving a low
output state. The Address/Data Bus pins encounter this condition between the last access of a read, and
the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at 50 pF
loads.
Figure 10. A.C. Test Load
Output Pin
CL = 50 pF for all signals
CL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EX256-PTQG100I | IC FPGA ANTIFUSE 12K 100-TQFP |
| EXPANDIO-USB-FS-DIL-28 | IC I/O EXPANDER USB 21B 28DIP |
| FIN1001M5 | IC DRIVER 3.3V LVDS HS SOT-23 |
| FIN1002M5 | RECEIVER 3.3V LVDS HS SOT-23 |
| FIN1017M | IC DRIVER 3.3V LVDS HS 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ET80960KA20512 | 功能描述:IC MPU I960KA 20MHZ 132-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| ET80960KB25512 | 功能描述:IC MPU I960KB 25MHZ 132-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| ET80CH012 | 制造商:Easy Braid Co 功能描述:CHISEL 30 1.20MM |
| ET80CH016 | 制造商:Easy Braid Co 功能描述:CHISEL 30 1.60MM |
| ET80CH024 | 制造商:Easy Braid Co 功能描述:CHISEL 30 2.40MM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。