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| 型號： | ES3986F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital-Audio Processor Product Brief |
| 中文描述： | 數(shù)字音頻處理器產(chǎn)品簡介 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 34K |
| 代理商： | ES3986F |
ESS Technology, Inc.
SAM0393-031201
3
ES3986 PRODUCT BRIEF
ES3986 PIN DESCRIPTIONS
ES3986 PIN DESCRIPTIONS
The ES3986 pins are listed and described in Table 1.
Table 1 ES3896 Pin Descriptions
Names
Pin Numbers
I/O
Definitions
VDD
1, 31, 51
I
Voltage supply for 2.5V.
RAS#
2
O
DRAM row address strobe (active low).
DWE#
3
O
DRAM write enable (active low).
DA[8:0]
4:12
O
DRAM multiplexed row and column address bus.
DBUS[15:0]
13:28
I/O
DRAM data bus.
RESET#
29
I
System reset (active low).
VSS
30, 50, 80, 100
I
Ground.
NC
32:41, 43, 44
—
No Connect.
CPUCLK
42
I
RISC and system clock input.
CPUCLK is used only if SEL_PLL[1:0] = 00.
AUX[7:0]
44:49, 54, 52,
53,
I/O
Auxiliary control pins (AUX0 and AUX1 are open collectors.)
LD[7:0]
55:62
I/O
RISC interface data bus.
LWR#
63
O
RISC interface write enable (active low).
LOE#
64
O
RISC interface output enable (active low).
LCS[3,1,0]#
65, 66, 67
O
RISC interface chip select (active low).
LA[17:0]
68:79, 82:87
O
RISC interface address bus.
VPP
81
I
Digital supply voltage for 5V.
ACLK
88
I/O
Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz)
AOUT/
SEL_PLL0
89
O
Dual-purpose pin. AOUT is the audio interface serial data output.
I
Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK
for the ES3986:
00 =
bypass PLL
01 =
54-MHz PLL
10 =
67.5-MHz PLL
11 =
81-MHz PLL.
ATCLK
90
I/O
Audio transmit bit clock.
ATFS/
SEL_PLL1
91
O
Dual-purpose pin. ATFS is the audio interface transmit frame sync.
I
Pins SEL_PLL[1:0] select phase-lock loop clock frequency CPUCLK for the ES3986.
(Refer to the SEL_PLL0 pin above for the settings.)
DA9/DOE#
92
O
Dual-purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column
address bus.
AIN
93
I
Audio interface serial data input.
ARCLK
94
I
Audio receive bit clock.
ARFS
95
I
Audio interface receive frame sync.
TDMCLK
96
I
TDM interface serial clock.
TDMDR
97
I
TDM interface serial data receive.
TDMFS
98
I
TDM interface frame sync.
CAS#
99
O
DRAM column address strobe bank 0 (active low).
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