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參數(shù)資料
| 型號(hào)： | EPM9560RC240-15 |
| 廠商： | Altera |
| 文件頁數(shù)： | 13/46頁 |
| 文件大小： | 0K |
| 描述： | IC MAX 9000 CPLD 560 240-RQFP |
| 產(chǎn)品變化通告： | Package Change 30/Jun/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Max® 9000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 35 |
| 宏單元數(shù)： | 560 |
| 門數(shù)： | 12000 |
| 輸入/輸出數(shù)： | 191 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-RQFP（32x32） |
| 包裝： | 托盤 |
| 其它名稱： | 544-2366 |
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20
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 9000 device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
A pulse time to erase, program, or read the EEPROM cells.
■
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM9560RC240-15YY | 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP |
| EPM9560RC240-20 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560RC304-15 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM9560RI208-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9560RI208-20 | 制造商:Altera Corporation 功能描述:IC MAX |
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