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| 型號： | EPM7128AETI144-7 |
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50
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in Table 11 on page 24. See
Figure 12 for more information on switching waveforms.
(2)
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(4)
This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
Operating conditions: VCCIO = 2.5 ± 0.2 V for commercial and industrial use.
(6)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in low-power mode.
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
The ICCINT value depends on the switching frequency and the application
logic. The ICCINT value is calculated with the following equation:
ICCINT =
(A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)
tRD
Register delay
1.6
2.0
2.7
3.2
ns
tCOMB
Combinatorial delay
1.6
2.0
2.7
3.2
ns
tIC
Array clock delay
2.7
3.4
4.5
5.4
ns
tEN
Register enable time
2.5
3.1
4.2
5.0
ns
tGLOB
Global control delay
1.1
1.4
1.8
2.2
ns
tPRE
Register preset time
2.3
2.9
3.8
4.6
ns
tCLR
Register clear time
2.3
2.9
3.8
4.6
ns
tPIA
PIA delay
1.3
1.6
2.1
2.6
ns
tLPA
Low-power adder
11.0
10.0
ns
Table 27. EPM7256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPM7256AEFC100-10 | |
| EPM7256AEFC100-5 | |
| EPM7256AEFC100-7 | |
| EPM7256AEFC256-10 | |
| EPM7256AEFC256-5 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7128AETI144-7N | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7128AEUC169-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AFC100-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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