參數(shù)資料
型號: EPM7032AETI44-5
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 5 ns, PQFP44
封裝: TQFP-44
文件頁數(shù): 49/51頁
文件大?。?/td> 1559K
代理商: EPM7032AETI44-5
Altera Corporation
601
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Macrocells
The MAX 7000A macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows the MAX 7000A
macrocell.
Figure 2. MAX 7000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR
gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
s
Shareable expanders, which are inverted product terms that are fed
back into the logic array
s
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Term
Select
Matrix
36 Signals
from PIA
16 Expander
Product Terms
LAB Local Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear
Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D
Q
ENA
,,
Register
Bypass
To I/O
Control
Block
,,,
,,
From
I/O pin
To PIA
Programmable
Register
Fast Input
Select
VCC
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