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參數(shù)資料
| 型號： | EPM240T100C5N |
| 廠商： | Altera |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAX II CPLD 240 LE 100-TQFP |
| 產(chǎn)品變化通告： | Bond Wire Change 4/Sept/2008 |
| 標準包裝： | 270 |
| 系列： | MAX® II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.7ns |
| 電壓電源 - 內(nèi)部： | 2.5V，3.3V |
| 邏輯元件/邏輯塊數(shù)目： | 240 |
| 宏單元數(shù)： | 192 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 603 (CN2011-ZH PDF) |
| 其它名稱： | 544-1964 EPM240T100C5N-ND |
1–2
Chapter 1: Introduction
Features
Table 1–1 shows the MAX II family features.
f For more information about equivalent macrocells, refer to the MAX II Logic Element to
Macrocell Conversion Methodology white paper.
MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with
–3 being the fastest. Similarly, MAX IIZ devices are available in three speed grades: –6,
–7, and –8, with –6 being the fastest. These speed grades represent the overall relative
performance, not any specific timing parameter. For propagation delay timing
numbers within each speed grade and density, refer to the DC and Switching
Characteristics chapter in the MAX II Device Handbook.
Table 1–2 shows MAX II device speed-grade offerings.
Table 1–1. MAX II Family Features
Feature
EPM240
EPM240G
EPM570
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
LEs
240
570
1,270
2,210
240
570
Typical Equivalent Macrocells
192
440
980
1,700
192
440
Equivalent Macrocell Range
128 to 240
240 to 570
570 to 1,270
1,270 to 2,210
128 to 240
240 to 570
UFM Size (bits)
8,192
Maximum User I/O pins
80
160
212
272
80
160
t
PD1 (ns) (1)
4.7
5.4
6.2
7.0
7.5
9.0
f
CNT (MHz) (2)
304
152
t
SU (ns)
1.7
1.2
2.3
2.2
t
CO (ns)
4.3
4.5
4.6
6.5
6.7
Notes to Table 1–1:
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic
implemented in a single LUT and LAB that is adjacent to the output pin.
(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.
Table 1–2. MAX II Speed Grades
Device
Speed Grade
–3
–4
–5
–6
–7
–8
EPM240
EPM240G
vv
v
———
EPM570
EPM570G
vv
v
———
EPM1270
EPM1270G
vv
v
———
EPM2210
EPM2210G
vv
v
———
EPM240Z
—
vvv
EPM570Z
———
vvv
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPM240T100C5N-LJ163174100 | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100C5NRR | 制造商:Altera 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100C5RR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100I | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM240T100I5 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX II 192 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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