參數(shù)資料
型號(hào)： EPL43102
英文描述： Graphic STN LCD Drivers with Built-in RAM
中文描述： 圖形STN液晶顯示器驅(qū)動(dòng)器，內(nèi)置內(nèi)存
文件頁(yè)數(shù)： 7/64頁(yè)
文件大?。?/td> 280K
代理商： EPL43102
43 COM / 102 SEG LCD DRIVER
The information in this document is subject to change without notice.
10
FUNCTION DESCRIPTION
SYSTEM INTERFACE
Figure 2
MPU interface
The EPL43102 has two chip select pin /CS1 and CS2. In case of /CS1="L" and CS2=”H”,
the interface with MPU is available. When the chip select pin is inactive (Other /CS1 and
CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or /WR
inputs are not effective. If the serial interface has been selected, the shift register and
counter are both reset.
However, the reset is always operated in any conditions of /CS1 and CS2.
P/S
C68
A0
/WR /RD
D0~D4
D5
D6
D7
Serial
Mode
(L)
SPI interface
( - )
A0
R/W
-
*
SDO SCK
SDI
80-series (L)
A0
/WR /RD
D0~D7
Parallel
mode
(H)
68-series (H)
A0
R/W
E
D0~D7
NOTE: * : Don’ t care ("High", "Low" or "Open")
- : Fixed “ High” (VDD) or “ Low” (VSS)
The EPL43102 can be operated with serial interface (SPI) and parallel interface
(80-series or 68-series) is selected by P/S pin.
I/O Buffer
( Serial/Parallel )
MPU Interface
Bus holder
INSTRUCTION
REGISTER
STATUS
REGISTER
INSTRUCTION
DECODER
D7
D6 D5
D4 D3 D2
D1
D0
/CS1 CS2 A0 /RD /WR C86 P/S /RES
(E) (R/W)
(SDI)(SCK)(SDO)
BUSY
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