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參數(shù)資料
| 型號(hào)： | EPF8452ALC84-3 |
| 廠商： | Altera |
| 文件頁數(shù)： | 60/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 8000A FPGA 4K 84-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | FLEX 8000 |
| LAB/CLB數(shù)： | 42 |
| 邏輯元件/單元數(shù)： | 336 |
| 輸入/輸出數(shù)： | 68 |
| 門數(shù)： | 4000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.31x29.31） |
| 其它名稱： | 544-2256-5 |
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Altera Corporation
7
FLEX 8000 Programmable Logic Device Family Data Sheet
FL
EX
800
0
3
Each LAB provides four control signals that can be used in all eight LEs.
Two of these signals can be used as clocks, and the other two for
clear/preset control. The LAB control signals can be driven directly from
a dedicated input pin, an I/O pin, or any internal signal via the LAB local
interconnect. The dedicated inputs are typically used for global clock,
clear, or preset signals because they provide synchronous control with
very low skew across the device. FLEX 8000 devices support up to four
individual global clock, clear, or preset control signals. If logic is required
on a control signal, it can be generated in one or more LEs in any LAB and
driven into the local interconnect of the target LAB.
Logic Element
The logic element (LE) is the smallest unit of logic in the FLEX 8000
architecture, with a compact size that provides efficient logic utilization.
Each LE contains a 4-input LUT, a programmable flipflop, a carry chain,
and cascade chain. Figure 3 shows a block diagram of an LE.
Figure 3. FLEX 8000 LE
The LUT is a function generator that can quickly compute any function of
four variables. The programmable flipflop in the LE can be configured for
D, T, JK, or SR operation. The clock, clear, and preset control signals on the
flipflop can be driven by dedicated input pins, general-purpose I/O pins,
or any internal logic. For purely combinatorial functions, the flipflop is
bypassed and the output of the LUT goes directly to the output of the LE.
LABCTRL3
LABCTRL4
DATA1
DATA2
DATA3
DATA4
LABCTRL1
LABCTRL2
Carry-In
LE-Out
Clock
Select
Carry-Out
PRN
CLRN
DQ
DFF
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8452ALC844 | 制造商:ALTERA 功能描述:New |
| EPF8452ALC84-4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 8000 42 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8452ALC844N | 制造商:Altera Corporation 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 84-Pin PLCC 制造商:Altera 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 84-Pin PLCC |
| EPF8452ALC84-4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 8000 42 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8452ALC84-6 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 84 Pin, Plastic, PLCC |
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