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參數(shù)資料
| 型號(hào)： | EPF8282ATC100-3 |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 59/62頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 8000A FPGA 2.5K 100-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 270 |
| 系列： | FLEX 8000 |
| LAB/CLB數(shù)： | 26 |
| 邏輯元件/單元數(shù)： | 208 |
| 輸入/輸出數(shù)： | 78 |
| 門(mén)數(shù)： | 2500 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 產(chǎn)品目錄頁(yè)面： | 602 (CN2011-ZH PDF) |
| 其它名稱： | 544-2253 |
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62
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Perform a complete thermal analysis before committing a design to this device package. See Application Note 74
(Evaluating Power for Altera Devices) for more information.
(2)
This pin is a dedicated pin and is not available as a user I/O pin.
(3)
SDOUT
will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the
MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and
use SDOUT as a user I/O pin.
(4)
If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.
(5)
JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.
(6)
If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration.
(7)
TRST
is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.
(8)
Pin 52 is a VCC pin on EPF8452A devices only.
(9)
The user I/O pin count includes dedicated input pins and all I/O pins.
(10) Unused dedicated inputs should be tied to ground on the board.
(11) SDOUT does not exist in the EPF8636GC192 device.
(12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.
(13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.
(14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is
not used, TDI, TCK, TMS, and TRST should be tied to GND.
Revision
History
The information contained in the FLEX 8000 Programmable Logic Device
Family Data Sheet version 11.1 supersedes information published in
previous versions. The FLEX 8000 Programmable Logic Device Family Data
Sheet version 11.1 contains the following change: minor textual updates.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8282ATC100-3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8282ATC1004 | 制造商:ALTERA 功能描述:* |
| EPF8282ATC100-4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8282ATC100-4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8282ATI100-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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