參數(shù)資料
| 型號： | EPF6024AQC240-1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 6000 FPGA 24K 240-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 96 |
| 系列： | FLEX 6000 |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 1960 |
| 輸入/輸出數(shù)： | 199 |
| 門數(shù)： | 24000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
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Altera Corporation
19
FLEX 6000 Programmable Logic Device Family Data Sheet
A row channel can be driven by an LE or by one of two column channels.
These three signals feed a 3-to-1 multiplexer that connects to six specific
row channels. Row channels drive into the local interconnect via
multiplexers.
Each column of LABs is served by a dedicated column interconnect. The
LEs in an LAB can drive the column interconnect. The LEs in an LAB, a
column IOE, or a row interconnect can drive the column interconnect. The
column interconnect can then drive another row’s interconnect to route
the signals to other LABs in the device. A signal from the column
interconnect must be routed to the row interconnect before it can enter an
LAB.
Each LE has a FastTrack Interconnect output and a local output. The
FastTrack interconnect output can drive six row and two column lines
directly; the local output drives the local interconnect. Each local
interconnect channel driven by an LE can drive four row and two column
channels. This feature provides additional flexibility, because each LE can
drive any of ten row lines and four column lines.
In addition, LEs can drive global control signals. This feature is useful for
distributing internally generated clock, asynchronous clear, and
asynchronous preset signals. A pin-driven global signal can also drive
data signals, which is useful for high-fan-out data signals.
Each LAB drives two groups of local interconnects, which allows an LE to
drive two LABs, or 20 LEs, via the local interconnect. The row-to-local
multiplexers are used more efficiently, because the multiplexers can now
drive two LABs. Figure 10 shows how an LAB connects to row and
column interconnects.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPF6024AQC240-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQI2083 | 制造商:Altera Corporation 功能描述: |
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