Notes: (1) To implement the ClockLock and ClockBoost circu" />
參數資料
型號： EPF10K50VBC356-4N
廠商： Altera
文件頁數： 25/128頁
文件大?。?/td> 0K
描述： IC FLEX 10KV FPGA 50K 356-BGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 24
系列： FLEX-10K®
LAB/CLB數： 360
邏輯元件/單元數： 2880
RAM 位總計： 20480
輸入/輸出數： 274
門數： 116000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 356-BGA
供應商設備封裝： 356-BGA（35x35）
120
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
(2)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration, because the tLOCK value is less than the time required for configuration.
(3)
The tJITTER specification is measured under long-term observation.
Power
Consumption
The supply power (P) for FLEX 10K devices can be calculated with the
following equation:
P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO
Typical ICCSTANDBY values are shown as ICC0 in the FLEX 10K device DC
operating conditions tables on pages 46, 49, and 52 of this data sheet. The
ICCACTIVE value depends on the switching frequency and the application
logic. This value is calculated based on the amount of current that each LE
typically consumes. The PIO value, which depends on the device output
load characteristics and switching frequency, can be calculated using the
1
Compared to the rest of the device, the embedded array
consumes a negligible amount of power. Therefore, the
embedded array can be ignored when calculating supply
current.
The ICCACTIVE value is calculated with the following equation:
ICCACTIVE = K × fMAX × N × togLC ×
The parameters in this equation are shown below:
fCLKDEV1 Input deviation from user specification in MAX+PLUS II (ClockBoost clock
multiplication factor equals 1) (1)
±1MHz
fCLKDEV2 Input deviation from user specification in MAX+PLUS II (ClockBoost clock
multiplication factor equals 2) (1)
±0.5
MHz
tINCLKSTB Input clock stability (measured between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or ClockBoost to acquire lock (2)
10
s
tJITTER
Jitter on ClockLock or ClockBoost-generated clock (3)
1ns
tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock
40
50
60
%
Table 113. ClockLock & ClockBoost Parameters
(Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
A
MHz
LE
×
---------------------------
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EPF10K50VBI356-3 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 360 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VBI356-3N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 360 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VBI356-4 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 360 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VBI356-4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 360 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VFC484-1 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 360 LABs 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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