參數(shù)資料
型號(hào): EPF10K200EBC600-1
廠商: Altera
文件頁數(shù): 18/100頁
文件大?。?/td> 0K
描述: IC FLEX 10KE FPGA 200K 600-BGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 12
系列: FLEX-10KE®
LAB/CLB數(shù): 1248
邏輯元件/單元數(shù): 9984
RAM 位總計(jì): 98304
輸入/輸出數(shù): 470
門數(shù): 513000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 600-BGA
供應(yīng)商設(shè)備封裝: 600-BGA(45x45)
24
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Use 2 three-input LUTs: one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1
implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the Altera Compiler automatically selects the best
control signal implementation. Because the clear and preset functions are
active-low, the Compiler automatically assigns a logic high to an unused
clear or preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
Asynchronous clear
Asynchronous preset
Asynchronous clear and preset
Asynchronous load with clear
Asynchronous load with preset
Asynchronous load without clear or preset
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