參數(shù)資料
型號： EPF10K100EBC356-2X
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 78/120頁
文件大?。?/td> 1901K
代理商： EPF10K100EBC356-2X
60
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2)
Operating conditions: VCCIO = 3.3 V ± 10 % for commercial or industrial use.
(3)
Operating conditions: VCCIO = 2.5 V ± 5 % for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF10K100E, EPF10K130E, and EPF10K200S devices.
(4)
Operating conditions: VCCIO = 3.3 V.
(5)
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
(6)
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
(8)
These timing parameters are sample-tested only.
(9)
Contact Altera Applications for test circuit specifications and test conditions.
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, revision 2.2.
Tables 31 through 37 show EPF10K30E device internal and external
timing parameters.
Table 30. External Bidirectional Timing Parameters
Symbol
Parameter
Conditions
tINSUBIDIR
Setup time for bi-directional pins with global clock at same-row or same-
column LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
tINH
Hold time with global clock at IOE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register
C1= 35 pF
tXZBIDIR
Synchronous IOE output buffer disable delay
C1= 35 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate= off
C1= 35 pF
Table 31. EPF10K30E Device LE Timing Microparameters (Part 1 of 2)
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tLUT
0.7
0.8
1.1
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.6
0.7
1.0
ns
tPACKED
0.3
0.4
0.5
ns
tEN
0.6
0.8
1.0
ns
tCICO
0.1
0.2
ns
tCGEN
0.4
0.5
0.7
ns
tCGENR
0.1
0.2
ns
相關(guān)PDF資料
PDF描述
EPF10K100EBC356-3 Field Programmable Gate Array (FPGA)
EPF10K100EBC356-3DX ASIC
EPF10K100EBI356-1DX ASIC
EPF10K100EBI356-2DX ASIC
EPF10K100EBI356-3DX ASIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K100EBC356-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100EBC356-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EBI356-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EBI356-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EBI356-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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