參數(shù)資料
型號(hào): EPCS1SI8N
廠商: Altera
文件頁(yè)數(shù): 8/40頁(yè)
文件大小: 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 100
系列: EPCS
可編程類型: 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量: 1Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 604 (CN2011-ZH PDF)
其它名稱: 544-1242-5
Page 16
EPCS Device Memory Access
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 6 shows the instruction sequence of the write disable operation.
Read Status Operation
The read status operation code is b'0000 0101 and it lists the MSB first. You can use
the read status operation to read the status register. Figure 7 and Figure 8 show the
status bits in the status register of the EPCS devices.
Setting the write in progress bit to 1 indicates that the EPCS device is busy with a
write or erase cycle. Resetting the write in progress bit to 0 indicates no write or erase
cycle is in progress.
Figure 6. Write Disable Operation Timing Diagram
Figure 7. EPCS128, EPCS64, EPCS16, and EPCS4 Status Register Status Bits
Figure 8. EPCS1 Status Register Status Bits
nCS
DCLK
ASDI
DATA
01234567
Operation Code
High Impedance
Bit 7
Bit 0
Block Protect Bits [2..0]
Write In
Progress Bit
Write Enable
Latch Bit
BP2
BP1
BP0
WEL
WIP
Bit 7
Bit 0
Block Protect
Bits [1..0]
Write In
Progress Bit
Write Enable
Latch Bit
BP1
BP0
WEL
WIP
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