參數(shù)資料
型號: EPC1441TC32
廠商: Altera
文件頁數(shù): 9/26頁
文件大?。?/td> 0K
描述: IC CONFIG DEVICE 440KBIT 32-TQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 250
系列: EPC
可編程類型: OTP
存儲容量: 440kb
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
其它名稱: 544-1372
EPC1441TC32-ND
Timing Information
Page 17
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.
Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at
5.0 V.
Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V
Symbol
Parameter
Min
Typ
Max
Units
tPOR
POR delay (1)
——
200
ms
tOEZX
OE
high to DATA output enabled
80
ns
tCE
OE
high to first rising edge on DCLK
——
300
ns
tDSU
Data
setup time before rising edge on DCLK
30
ns
tDH
Data
hold time after rising edge on DCLK
0—
ns
tCO
DCLK
to DATA out
30
ns
tCDOE
DCLK
to DATA enable/disable
30
ns
fCLK
DCLK
frequency
2
4
10
MHz
tMCH
DCLK
high time for the first device in the configuration chain
50
125
250
ns
tMCL
DCLK
low time for the first device in the configuration chain
50
125
250
ns
tSCH
DCLK
high time for subsequent devices
50
ns
tSCL
DCLK
low time for subsequent devices
50
ns
tCASC
DCLK
rising edge to nCASC
25
ns
tCCA
nCS
to nCASC cascade delay
15
ns
tOEW
OE
low pulse width (reset) to guarantee counter reset
100
ns
tOEC
OE
low (reset) to DCLK disable delay
30
ns
tNRCAS
OE
low (reset) to nCASC delay
30
ns
Note to Table 9:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
tPOR
POR delay (1)
——
200
ms
tOEZX
OE
high to DATA output enabled
50
ns
tCE
OE
high to first rising edge on DCLK
——
200
ns
tDSU
Data
setup time before rising edge on DCLK
30
ns
tDH
Data
hold time after rising edge on DCLK
0—
ns
tCO
DCLK
to DATA out
20
ns
tCDOE
DCLK
to DATA enable/disable
20
ns
fCLK
DCLK
frequency
6.7
10
16.7
MHz
tMCH
DCLK
high time for the first device in the configuration chain
30
50
75
ns
tMCL
DCLK
low time for the first device in the configuration chain
30
50
75
ns
tSCH
DCLK
high time for subsequent devices
30
ns
tSCL
DCLK
low time for subsequent devices
30
ns
tCASC
DCLK
rising edge to nCASC
20
ns
tCCA
nCS
to nCASC cascade delay
10
ns
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